iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add SB_CARRY to ice40_opt test	Eddie Hung	2019-08-28	1	-3/+5
*	Add ice40_opt test	Eddie Hung	2019-08-28	1	-0/+24
*	Revert "Revert "Fix omode which inserts an output if none exists (otherwise a...	Eddie Hung	2019-08-28	1	-7/+8
*	Revert "Output "h" extension only if boxes"	Eddie Hung	2019-08-28	1	-32/+28
*	Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival	Eddie Hung	2019-08-28	2	-1/+48
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\| *	Trailing comma	Eddie Hung	2019-08-28	1	-1/+1
\| *	Adapt to $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-28	1	-3/+5
\| *	Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"	Eddie Hung	2019-08-28	1	-0/+45
* \|	Add arrival times for HX devices	Eddie Hung	2019-08-28	1	-21/+114
* \|	Specify ice40 family to cells_sim.v using define	Eddie Hung	2019-08-28	1	-1/+8
* \|	Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival	Eddie Hung	2019-08-28	5	-68/+20
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\| *	Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with	Eddie Hung	2019-08-28	1	-45/+0
\| *	Update box size and timings	Eddie Hung	2019-08-28	3	-12/+12
\| *	Update to new $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-28	1	-11/+8
* \|	Account for D port being a constant	Eddie Hung	2019-08-28	1	-4/+4
* \|	Merge branch 'eddie/xilinx_srl' into xaig_arrival	Eddie Hung	2019-08-28	13	-225/+819
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\| * \|	No need to replace Q of slice since $shiftx is autoremove-d	Eddie Hung	2019-08-28	1	-1/+0
\| * \|	More cleanup	Eddie Hung	2019-08-28	1	-12/+14
\| * \|	More cleanup	Eddie Hung	2019-08-28	1	-9/+6
\| * \|	Do not use default_params dict, hardcode default values, cleanup	Eddie Hung	2019-08-28	2	-25/+21
\| * \|	Add .gitignore	Eddie Hung	2019-08-28	1	-0/+3
\| * \|	Use test_pmgen for xilinx_srl	Eddie Hung	2019-08-28	1	-0/+57
\| * \|	Always generate if no match	Eddie Hung	2019-08-28	1	-1/+1
\| * \|	Rename test_pmgen arg xilinx_srl.{fixed,variable}	Eddie Hung	2019-08-28	1	-2/+2
\| * \|	Do not simplemap for variable test	Eddie Hung	2019-08-28	1	-2/+2
\| * \|	Add xilinx_srl test	Eddie Hung	2019-08-28	3	-0/+127
\| * \|	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-28	27	-347/+1438
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\| * \| \|	Missing close bracket	Eddie Hung	2019-08-26	1	-1/+1
\| * \| \|	Revert "In sat: 'x' in init attr should not override constant"	Eddie Hung	2019-08-26	3	-7/+1
\| * \| \|	Remove leftover header	Eddie Hung	2019-08-26	1	-1/+0
\| * \| \|	Improve xilinx_srl.fixed generate, add .variable generate	Eddie Hung	2019-08-26	1	-26/+75
\| * \| \|	Account for maxsubcnt overflowing	Eddie Hung	2019-08-26	1	-1/+1
\| * \| \|	Add xilinx_srl_pm.variable to test_pmgen	Eddie Hung	2019-08-26	1	-0/+2
\| * \| \|	Populate generate for xilinx_srl.fixed pattern	Eddie Hung	2019-08-26	1	-22/+54
\| * \| \|	Add xilinx_srl_fixed, fix typos	Eddie Hung	2019-08-26	1	-2/+6
\| * \| \|	Merge branch 'master' into eddie/xilinx_srl	Eddie Hung	2019-08-26	4	-28/+125
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\| * \| \| \|	Create new $__XILINX_SHREG_ cell for variable length too	Eddie Hung	2019-08-23	1	-31/+30
\| * \| \| \|	Do not allow Q of last cell of variable length SRL to be (* keep *)	Eddie Hung	2019-08-23	1	-0/+1
\| * \| \| \|	Also add first.Q to chain_bits since variable length	Eddie Hung	2019-08-23	1	-0/+1
\| * \| \| \|	Do not enforce !EN_POLARITY on $dffe	Eddie Hung	2019-08-23	1	-2/+0
\| * \| \| \|	Create new cell for fixed length SRL	Eddie Hung	2019-08-23	1	-14/+22
\| * \| \| \|	Cleanup FDRE matching	Eddie Hung	2019-08-23	1	-45/+19
\| * \| \| \|	Oops don't need a finally block	Eddie Hung	2019-08-23	1	-5/+0
\| * \| \| \|	Keep track of bits in variable length chain, to check for taps	Eddie Hung	2019-08-23	1	-0/+12
\| * \| \| \|	Don't forget $dff has no EN	Eddie Hung	2019-08-23	1	-2/+4
\| * \| \| \|	Same for variable length	Eddie Hung	2019-08-23	1	-2/+10
\| * \| \| \|	Filter on en_port for fixed length	Eddie Hung	2019-08-23	1	-4/+24
\| * \| \| \|	Check clock is consistent	Eddie Hung	2019-08-23	1	-5/+25
\| * \| \| \|	Fix last_cell.D	Eddie Hung	2019-08-23	1	-2/+1
\| * \| \| \|	Revert "Add a unique argument to pmgen's nusers()"	Eddie Hung	2019-08-23	1	-8/+4