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authorEddie Hung <eddie@fpgeh.com>2019-08-23 15:08:49 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-23 15:08:49 -0700
commitc76261878340bc87fc5ab2f5ac8c7a1fb5a1b3a2 (patch)
tree37ea9094f1a5dc229773a55c83fd8205343660ed
parentca5de78e762172a6c602470560354eff1de73cf7 (diff)
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Fix last_cell.D
-rw-r--r--passes/pmgen/xilinx_srl.cc3
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index ef3e61661..c0c827a25 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -141,8 +141,7 @@ void run_variable(xilinx_srl_pm &pm)
if (c->type.in(ID($dff), ID($dffe))) {
auto &Q = last_cell->connections_.at(ID(Q));
Q = Q[last_slice];
- auto &D = first_cell->connections_.at(ID(D));
- D = D[first_slice];
+ last_cell->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
}
if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {