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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 18:15:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 18:15:24 -0700 |
| commit | a048fc93e8cf187b28bd5ed924643671b9314678 (patch) | |
| tree | 4979491b5cd2398afebae13b95188640a656511f | |
| parent | ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e (diff) | |
| download | yosys-a048fc93e8cf187b28bd5ed924643671b9314678.tar.gz yosys-a048fc93e8cf187b28bd5ed924643671b9314678.tar.bz2 yosys-a048fc93e8cf187b28bd5ed924643671b9314678.zip | |
Do not allow Q of last cell of variable length SRL to be (* keep *)
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 76134de1a..cfa1cacfb 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -176,6 +176,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() + select !port(first, \Q)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(first, \Q)) select nusers(port(first, \Q)[idx]) <= 2 index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] |