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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 18:14:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 18:14:06 -0700 |
| commit | ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e (patch) | |
| tree | 3ba26e0e0e9e75eb5da8e8e22984c02f650f5bb0 | |
| parent | 70ce3d067010d67154c3cd5437caa16b4c8ca195 (diff) | |
| download | yosys-ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e.tar.gz yosys-ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e.tar.bz2 yosys-ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e.zip | |
Also add first.Q to chain_bits since variable length
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index d41bd3be9..76134de1a 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -196,6 +196,7 @@ code clk_port en_port en_port = \EN; else log_abort(); + chain_bits.insert(port(first, \Q)[slice]); chain.emplace_back(first, slice); subpattern(tail); finally |