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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:26:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:26:08 -0700 |
| commit | 2e9e745efa03363f9f0d5cc47696401d55a8e5d2 (patch) | |
| tree | 408b58843092143db3328ddc9fb261f9bc4d7e22 | |
| parent | 975aaf190f0bbbeacc253397ccada6889c69e8f7 (diff) | |
| download | yosys-2e9e745efa03363f9f0d5cc47696401d55a8e5d2.tar.gz yosys-2e9e745efa03363f9f0d5cc47696401d55a8e5d2.tar.bz2 yosys-2e9e745efa03363f9f0d5cc47696401d55a8e5d2.zip | |
Do not simplemap for variable test
| -rw-r--r-- | tests/xilinx/xilinx_srl.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys index 4e3c44a98..b8df0e55a 100644 --- a/tests/xilinx/xilinx_srl.ys +++ b/tests/xilinx/xilinx_srl.ys @@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test prep design -save gold -simplemap t:$dff t:$dffe xilinx_srl -variable opt #stat # show -width # write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i select -assert-count 2 t:$__XILINX_SHREG_ design -stash gate |