| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | IS_C_INVERTED | Eddie Hung | 2019-06-03 | 1 | -4/+4 |
| * | Fix `ifndef | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
| * | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) | Eddie Hung | 2019-06-03 | 4 | -8/+8 |
| * | Assert that box_unique_id is indeed unique | Eddie Hung | 2019-06-03 | 1 | -2/+3 |
| * | Remove dupe | Eddie Hung | 2019-06-03 | 1 | -7/+7 |
| * | Skip internal modules when generating box_unique_id | Eddie Hung | 2019-06-03 | 1 | -0/+1 |
| * | When creating new holes cell, inherit parameters too | Eddie Hung | 2019-06-03 | 1 | -1/+3 |
| * | Ooopsie | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
| * | Consistent with xilinx | Eddie Hung | 2019-06-03 | 3 | -4/+4 |
| * | Add flops as blackboxes | Eddie Hung | 2019-05-31 | 2 | -0/+27 |
| * | Add FD*E_1 -> FD*E techmap rules | Eddie Hung | 2019-05-31 | 1 | -5/+31 |
| * | Techmap flops before ABC again | Eddie Hung | 2019-05-31 | 1 | -4/+4 |
| * | parse_xaiger to cope with flops | Eddie Hung | 2019-05-31 | 2 | -83/+123 |
| * | ABC9 to understand flops | Eddie Hung | 2019-05-31 | 1 | -46/+27 |
| * | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 5 | -15/+99 |
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| | * | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 2 | -6/+52 |
| | * | Move clean from aigerparse to abc9 | Eddie Hung | 2019-04-23 | 2 | -2/+1 |
| | * | Use nonblocking | Eddie Hung | 2019-04-23 | 1 | -1/+1 |
| | * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-22 | 8 | -41/+382 |
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| | | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 8 | -41/+382 |
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| | * | | | Tidy up | Eddie Hung | 2019-04-22 | 2 | -7/+1 |
| | * | | | Revert "Temporarily remove 'r' extension" | Eddie Hung | 2019-04-22 | 2 | -7/+95 |
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| * | | | Throw out unused code inherited from abc | Eddie Hung | 2019-05-31 | 1 | -212/+3 |
| * | | | Fix issue where keep signal became PI, but also box was adding CI driver | Eddie Hung | 2019-05-30 | 1 | -5/+19 |
| * | | | read_xaiger() to name box signals | Eddie Hung | 2019-05-30 | 1 | -4/+8 |
| * | | | Fix spelling | Eddie Hung | 2019-05-30 | 1 | -1/+1 |
| * | | | Remove whitebox attribute from DRAMs for now | Eddie Hung | 2019-05-30 | 1 | -2/+2 |
| * | | | Do not re-sort box_module ports | Eddie Hung | 2019-05-30 | 1 | -4/+6 |
| * | | | Remove whitespace | Eddie Hung | 2019-05-30 | 1 | -1/+0 |
| * | | | Revert "Re-enable &dc2" | Eddie Hung | 2019-05-30 | 1 | -1/+1 |
| * | | | Do not double count LUT1s | Eddie Hung | 2019-05-30 | 1 | -1/+0 |
| * | | | Carry in/out to be the last input/output for chains to be preserved | Eddie Hung | 2019-05-30 | 4 | -12/+91 |
| * | | | Re-enable &dc2 | Eddie Hung | 2019-05-30 | 1 | -1/+1 |
| * | | | Reduce -W to 160 | Eddie Hung | 2019-05-29 | 1 | -1/+1 |
| * | | | Some more realistic delays... | Eddie Hung | 2019-05-29 | 1 | -7/+7 |
| * | | | Erase all boxes before stitching | Eddie Hung | 2019-05-29 | 1 | -27/+30 |
| * | | | Call &if with -W 250 | Eddie Hung | 2019-05-29 | 1 | -1/+6 |
| * | | | Bump ABC | Eddie Hung | 2019-05-29 | 1 | -1/+1 |
| * | | | Rename to #23 | Eddie Hung | 2019-05-29 | 1 | -3/+3 |
| * | | | Add abc_test024 | Eddie Hung | 2019-05-29 | 1 | -6/+19 |
| * | | | Fix abc_test024 | Eddie Hung | 2019-05-29 | 1 | -4/+5 |
| * | | | Add some debug to abc9 | Eddie Hung | 2019-05-29 | 1 | -1/+19 |
| * | | | Add abc9_test022 | Eddie Hung | 2019-05-28 | 1 | -0/+22 |
| * | | | Fix for abc9_test022 | Eddie Hung | 2019-05-28 | 1 | -2/+6 |
| * | | | Small improvement | Eddie Hung | 2019-05-28 | 1 | -4/+2 |
| * | | | From master | Eddie Hung | 2019-05-28 | 1 | -1/+1 |
| * | | | From master | Eddie Hung | 2019-05-28 | 1 | -1/+1 |
| * | | | Typo | Eddie Hung | 2019-05-28 | 1 | -1/+1 |
| * | | | Update from master | Eddie Hung | 2019-05-28 | 5 | -64/+59 |
| * | | | Update README.md from master | Eddie Hung | 2019-05-28 | 1 | -3/+3 |
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index : iCE40/yosys | |
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