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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 13:42:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 13:42:06 -0700 |
| commit | 91c3afcab723d85d3c6931561cb13ad7b70e7e5c (patch) | |
| tree | 8cecc79896264f3c653d03ed506b146382e8f429 | |
| parent | 4df4a97ffa77ad75013a0b616f25a2be4fc77e34 (diff) | |
| download | yosys-91c3afcab723d85d3c6931561cb13ad7b70e7e5c.tar.gz yosys-91c3afcab723d85d3c6931561cb13ad7b70e7e5c.tar.bz2 yosys-91c3afcab723d85d3c6931561cb13ad7b70e7e5c.zip | |
Use nonblocking
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 40e54f9f0..40972766d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in always @(posedge C) Q <= D; `else - always @* Q = D; + always @* Q <= D; `endif endmodule |