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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-29 15:21:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-29 15:21:41 -0700 |
| commit | ecaa7856e96dad8de5ef162bb1c9c5814de5254f (patch) | |
| tree | 7f14c3c1f799f8990346d200d8727d4089af2505 | |
| parent | 92197326b8fa406e94c952cfcb778611642a3e00 (diff) | |
| download | yosys-ecaa7856e96dad8de5ef162bb1c9c5814de5254f.tar.gz yosys-ecaa7856e96dad8de5ef162bb1c9c5814de5254f.tar.bz2 yosys-ecaa7856e96dad8de5ef162bb1c9c5814de5254f.zip | |
Add some debug to abc9
| -rw-r--r-- | passes/techmap/abc9.cc | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 328f0e3c3..41ab9abea 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -423,6 +423,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); +#if 0 + std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig"); + std::ifstream ifs; + ifs.open(buffer); + if (ifs.fail()) + log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); + buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); + log_assert(!design->module("$__abc9__")); + AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); + reader.parse_xaiger(); + ifs.close(); + Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v")); + design->remove(design->module("$__abc9__")); +#endif + design->selection_stack.pop_back(); // Now 'unexpose' those wires by undoing @@ -540,9 +555,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_assert(!design->module("$__abc9__")); AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); reader.parse_xaiger(); - ifs.close(); +#if 0 + Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v")); +#endif + log_header(design, "Re-integrating ABC9 results.\n"); RTLIL::Module *mapped_mod = design->module("$__abc9__"); if (mapped_mod == NULL) |