| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | Move muxpack from passes/techmap to passes/opt | Eddie Hung | 2019-06-06 | 3 | -1/+1 | |
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| | * | | | | Update doc | Eddie Hung | 2019-06-06 | 1 | -4/+5 | |
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| | * | | | | Add to CHANGELOG | Eddie Hung | 2019-06-06 | 1 | -0/+1 | |
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| | * | | | | One more and tidy up | Eddie Hung | 2019-06-06 | 2 | -6/+28 | |
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| | * | | | | Add a few more special case tests | Eddie Hung | 2019-06-06 | 2 | -0/+51 | |
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| | * | | | | Add tests, fix for != | Eddie Hung | 2019-06-06 | 3 | -9/+110 | |
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| | * | | | | Missing file | Eddie Hung | 2019-06-06 | 1 | -0/+232 | |
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| | * | | | | Initial adaptation of muxpack from shregmap | Eddie Hung | 2019-06-06 | 1 | -0/+1 | |
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| | * | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 14 | -10/+279 | |
| | |\ \ \ | | | | | | | | | | | Added support for parsing attributes on port connections. | |||||
| | | * | | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | | * | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵ | Maciej Kurc | 2019-06-04 | 4 | -0/+46 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | | * | | | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | | * | | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | * | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iob | David Shah | 2019-06-06 | 1 | -0/+15 | |
| | |\ \ \ \ | | | | | | | | | | | | | ECP5: implement most Diamond I/O buffer primitives | |||||
| | | * | | | | ECP5: implement all Diamond I/O buffer primitives. | whitequark | 2019-06-06 | 1 | -0/+15 | |
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| | * | | | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | Fix typo in opt_rmdff causing register to be incorrectly removed | |||||
| | | * | | | | | Fix typo in opt_rmdff | Eddie Hung | 2019-06-05 | 1 | -2/+2 | |
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| | * | | | | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069 | Clifford Wolf | 2019-06-06 | 1 | -0/+5 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | Error out if no top module given before 'sim' | |||||
| | | * | | | | | | Error out if no top module given before 'sim' | Eddie Hung | 2019-06-05 | 1 | -0/+5 | |
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| | * / / / / / | Missing doc for -tech xilinx in shregmap | Eddie Hung | 2019-06-05 | 1 | -0/+3 | |
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| | * | | | | | Merge pull request #1067 from YosysHQ/clifford/fix1065 | Eddie Hung | 2019-06-05 | 1 | -1/+1 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | Suppress driver-driver conflict warning for unknown cell types | |||||
| * | | | | | | | shregmap -tech xilinx_static to handle INIT | Eddie Hung | 2019-06-05 | 1 | -22/+32 | |
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| * | | | | | | | Continue support for ShregmapTechXilinx7Static | Eddie Hung | 2019-06-05 | 1 | -30/+81 | |
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| * | | | | | | | Update abc attributes on FD*E_1 | Eddie Hung | 2019-06-05 | 1 | -6/+26 | |
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| * | | | | | | | Cleanup | Eddie Hung | 2019-06-05 | 2 | -17/+0 | |
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| * | | | | | | | Call shregmap -tech xilinx_static | Eddie Hung | 2019-06-05 | 1 | -1/+1 | |
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| * | | | | | | | Revert "Move ff_map back after ABC for shregmap" | Eddie Hung | 2019-06-05 | 1 | -4/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9b9bd4e19f3da363eb3c90ef27ace282716d2e06. | |||||
| * | | | | | | | Add -tech xilinx_static | Eddie Hung | 2019-06-05 | 1 | -2/+13 | |
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| * | | | | | | | Refactor to ShregmapTechXilinx7Static | Eddie Hung | 2019-06-05 | 1 | -46/+86 | |
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| * | | | | | | | shregmap -tech xilinx_dynamic to work -params and -enpol | Eddie Hung | 2019-06-05 | 1 | -6/+26 | |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-05 | 3 | -28/+95 | |
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| | * | | | | | | Merge pull request #1066 from YosysHQ/clifford/fix1056 | Clifford Wolf | 2019-06-05 | 1 | -1/+0 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | Remove yosys_banner() from python wrapper init | |||||
| | | * | | | | | | Remove yosys_banner() from python wrapper init, fixes #1056 | Clifford Wolf | 2019-06-05 | 1 | -1/+0 | |
| | | | |_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | Major rewrite of wire selection in setundef -init | Clifford Wolf | 2019-06-05 | 1 | -30/+89 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | Indent fix | Clifford Wolf | 2019-06-05 | 1 | -23/+25 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | Merge pull request #999 from jakobwenzel/setundefInitFix | Clifford Wolf | 2019-06-05 | 1 | -16/+23 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | initialize more registers in setundef -init | |||||
| | | * | | | | | | initialize more registers in setundef -init | Jakob Wenzel | 2019-05-09 | 1 | -16/+23 | |
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| | * | | | | | | | Fix typo in fmcombine log message, fixes #1063 | Clifford Wolf | 2019-06-05 | 1 | -2/+2 | |
| | | |/ / / / / | |/| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux | Eddie Hung | 2019-06-05 | 2 | -2/+2 | |
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| | * | | | | | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065 | Clifford Wolf | 2019-06-05 | 1 | -1/+1 | |
| | |/ / / / / | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Merge pull request #1062 from tux3/patch-1 | Clifford Wolf | 2019-06-04 | 1 | -1/+1 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | README.md: Missing formatting for <tag> | |||||
| | | * | | | | | README.md: Missing formatting for <tag> | Tux3 | 2019-06-04 | 1 | -1/+1 | |
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| * | | | | | | Rename shregmap -tech xilinx -> xilinx_dynamic | Eddie Hung | 2019-06-04 | 2 | -6/+6 | |
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| * | | | | | | Add log_assert to ensure no loops | Eddie Hung | 2019-06-04 | 1 | -1/+15 | |
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| * | | | | | | Only toposort builtin and abc types | Eddie Hung | 2019-06-04 | 1 | -6/+9 | |
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| * | | | | | | Add space between -D and _ABC | Eddie Hung | 2019-06-04 | 1 | -2/+2 | |
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| * | | | | | | Add (* abc_flop_q *) to brams_bb.v | Eddie Hung | 2019-06-04 | 1 | -8/+8 | |
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| * | | | | | | Fix name clash | Eddie Hung | 2019-06-04 | 1 | -11/+11 | |
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| * | | | | | | Add mux_map.v for wide mux | Eddie Hung | 2019-06-04 | 4 | -30/+82 | |
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| * | | | | | | Move ff_map back after ABC for shregmap | Eddie Hung | 2019-06-03 | 1 | -4/+4 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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