From d06258f74f724ea3ed26ec9341dd64a51e320ccf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 1 Feb 2014 13:50:23 +0100
Subject: Added constant size expression support of sized constants

---
 README | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'README')

diff --git a/README b/README
index f0c9bc747..ee5eb7979 100644
--- a/README
+++ b/README
@@ -275,6 +275,10 @@ Verilog Attributes and non-standard features
   always block: "assert(<expression>);". It is transformed to a $assert cell
   that is supported by the "sat" and "write_btor" commands.
 
+- Sized constants (the syntax <size>'s?[bodh]<value>) support constant
+  expressions as <size>. If the expresion is not a simple identifier, it
+  must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
+
 
 Workarounds for known build problems
 ====================================
-- 
cgit v1.2.3