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Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -275,6 +275,10 @@ Verilog Attributes and non-standard features always block: "assert(<expression>);". It is transformed to a $assert cell that is supported by the "sat" and "write_btor" commands. +- Sized constants (the syntax <size>'s?[bodh]<value>) support constant + expressions as <size>. If the expresion is not a simple identifier, it + must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 + Workarounds for known build problems ==================================== |