iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07	1	-18/+17
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22	1	-0/+23
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21	1	-21/+27
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21	1	-2/+4
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21	1	-17/+65
*	generated by cgit v1.2.3 (git 2.25.1) at 2025-04-21 12:21:50 +0000 ='insertions'>+6
*	disabling splice command in the script	Ahmed Irfan	2014-02-11	2	-2/+6
*	register output corrected	Ahmed Irfan	2014-02-11	1	-1/+1
*	added concat and slice cell translation	Ahmed Irfan	2014-02-11	3	-36/+59
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+22
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
*	Added BTOR backend README file	Clifford Wolf	2014-02-05	2	-1/+24
*	Added support for dump -append	Clifford Wolf	2014-02-04	1	-3/+12
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	2	-1/+6
*	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	Clifford Wolf	2014-01-26	1	-1/+5
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\| *	root bug corrected	Ahmed Irfan	2014-01-25	1	-1/+5
* \|	beautified write_intersynth	Johann Glaser	2014-01-25	1	-0/+9
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*	removed regex include	Ahmed Irfan	2014-01-24	1	-1/+0
*	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24	1	-26/+52
*	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24	2	-2/+2
*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24	2	-0/+50
*	slice bug corrected	Ahmed Irfan	2014-01-20	1	-1/+1
*	assert feature	Ahmed Irfan	2014-01-20	1	-9/+40
*	verilog default options pull	Ahmed Irfan	2014-01-17	1	-28/+97
*	slice error corrected	Ahmed Irfan	2014-01-16	1	-5/+5
*	width issues	Ahmed Irfan	2014-01-15	1	-64/+87
*	BTOR backend	Ahmed Irfan	2014-01-14	1	-274/+328
*	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-01-03	2	-7/+9
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\| *	Updated manual/command-reference-manual.tex	Clifford Wolf	2013-12-28	1	-1/+1
\| *	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-6/+8
* \|	btor	Ahmed Irfan	2014-01-03	2	-0/+774
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	2	-2/+2
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	3	-18/+24
*	Fixed gentb_constant handling in autotest backend	Clifford Wolf	2013-12-04	1	-2/+2
*	Added dump -m and -n options	Clifford Wolf	2013-11-29	2	-54/+89
*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24	1	-4/+6
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	1	-1/+1
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-2/+0
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24	1	-6/+6
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	3	-0/+15
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	5	-14/+14
*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21	1	-1/+44
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-0/+1
*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09	1	-1/+1
*	Improved comments on topological sort in edif backend	Clifford Wolf	2013-11-04	1	-3/+4
*	Added simple topological sort to edif backend	Clifford Wolf	2013-11-03	1	-2/+30
*	Write yosys version to output files	Clifford Wolf	2013-11-03	5	-6/+10
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-11-03	1	-3/+5
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\| *	Ignore explicit unconnected ports in intersynth backend	Clifford Wolf	2013-11-03	1	-3/+5