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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-03 09:00:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-03 09:00:51 +0100 |
| commit | 4a60e5842d6a39c5b1917b2a6b5f7433b08280a3 (patch) | |
| tree | 827be650f287a3ab4fd38cc528cabc283824a288 /backends | |
| parent | d78a9dfb372654999916af46f35fe3914f960d9d (diff) | |
| download | yosys-4a60e5842d6a39c5b1917b2a6b5f7433b08280a3.tar.gz yosys-4a60e5842d6a39c5b1917b2a6b5f7433b08280a3.tar.bz2 yosys-4a60e5842d6a39c5b1917b2a6b5f7433b08280a3.zip | |
Ignore explicit unconnected ports in intersynth backend
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 83db8908c..a3f61eeb5 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -174,9 +174,11 @@ struct IntersynthBackend : public Backend { node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); for (auto &port : cell->connections) { RTLIL::SigSpec sig = sigmap(port.second); - conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width)); - celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); - node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); + if (sig.width != 0) { + conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width)); + celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); + node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); + } } for (auto ¶m : cell->parameters) { celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first)); |