| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: handle record conversion | Tristan Gingold | 2022-10-14 | 1 | -0/+3 |
| * | synth-vhdl_expr: support alias in indexed names | Tristan Gingold | 2022-10-14 | 1 | -1/+2 |
| * | synth: avoid extra conversion during alias elaboration | Tristan Gingold | 2022-10-14 | 1 | -6/+4 |
| * | simul: fix spurious error about multiple drivers | Tristan Gingold | 2022-10-14 | 1 | -0/+2 |
| * | simul: handle delayed attribute | Tristan Gingold | 2022-10-14 | 2 | -6/+66 |
| * | synth: handle alias of access objects. | Tristan Gingold | 2022-10-13 | 1 | -1/+1 |
| * | simul: handle last_event and last_active | Tristan Gingold | 2022-10-13 | 3 | -4/+114 |
| * | elab-vhd_expr: handle more cases in exec_type_of_object | Tristan Gingold | 2022-10-13 | 1 | -1/+4 |
| * | simul-vhdl_simul: keep default value of collapsed signals | Tristan Gingold | 2022-10-13 | 1 | -1/+10 |
| * | simul-vhdl_elab: fix crash on association with implicit signals | Tristan Gingold | 2022-10-13 | 1 | -1/+4 |
| * | simul: fix a crash due to missing stride | Tristan Gingold | 2022-10-13 | 1 | -5/+7 |
| * | synth-vhdl_stmts(synth_verification_unit): always set instance_pool. | Tristan Gingold | 2022-10-13 | 1 | -1/+3 |
| * | synth: fix crashes on scalar attribute with anonymous subtype. | Tristan Gingold | 2022-10-10 | 1 | -2/+2 |
| * | vhdl-canon: avoid a crash on optionnal condition. Fix #2212 | Tristan Gingold | 2022-10-10 | 1 | -1/+1 |
| * | simul: handle guarded concurrent assignments | Tristan Gingold | 2022-10-10 | 1 | -14/+32 |
| * | simul-vhdl_debug: handle state before elaboration | Tristan Gingold | 2022-10-10 | 1 | -0/+8 |
| * | vhdl-sem.adb(are_trees_equal): handle parenthesis expressions. | Tristan Gingold | 2022-10-08 | 1 | -0/+4 |
| * | simul: signal attributes in actuals | Tristan Gingold | 2022-10-06 | 1 | -2/+4 |
| * | simul: complete concurrent procedure calls | Tristan Gingold | 2022-10-06 | 3 | -29/+43 |
| * | simul: fix initial value of record signals | Tristan Gingold | 2022-10-06 | 1 | -2/+2 |
| * | simul: recompute object alias offsets | Tristan Gingold | 2022-10-06 | 1 | -1/+14 |
| * | simul: fix signal attribute or guard as actual in connections | Tristan Gingold | 2022-10-06 | 2 | -11/+15 |
| * | simul: improve debugger (display of signals value) | Tristan Gingold | 2022-10-06 | 4 | -38/+74 |
| * | simul: handle suspendable procedure call from sensitized process. | Tristan Gingold | 2022-10-05 | 2 | -3/+11 |
| * | elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205 | Tristan Gingold | 2022-10-04 | 1 | -2/+4 |
| * | synth: avoid crash on invalid hdl in psl. Fix #2204 | Tristan Gingold | 2022-10-03 | 3 | -17/+46 |
| * | translate, grt: add lib function for div and rem. | Tristan Gingold | 2022-10-02 | 6 | -8/+148 |
| * | synth: improve error recovery | Tristan Gingold | 2022-10-02 | 1 | -0/+3 |
| * | synth: detect division by 0, handle universal real/integer division | Tristan Gingold | 2022-10-02 | 1 | -3/+23 |
| * | synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174 | Tristan Gingold | 2022-10-02 | 1 | -18/+204 |
| * | synth: avoid a crash on literal overflow | Tristan Gingold | 2022-10-01 | 1 | -1/+10 |
| * | synth: avoid on crash on overflow in ranges | Tristan Gingold | 2022-10-01 | 1 | -0/+8 |
| * | synth: improve handling of individual generic associations | Tristan Gingold | 2022-10-01 | 1 | -17/+22 |
| * | simul: finalize empty procedures | Tristan Gingold | 2022-10-01 | 1 | -9/+11 |
| * | simul: minor rewrite | Tristan Gingold | 2022-10-01 | 1 | -3/+2 |
| * | simul: finalize declarations of procedure calls | Tristan Gingold | 2022-10-01 | 2 | -0/+6 |
| * | synth: handle read for floats | Tristan Gingold | 2022-09-30 | 2 | -8/+24 |
| * | synth: handle float-float conversions | Tristan Gingold | 2022-09-30 | 1 | -3/+14 |
| * | simul: handle stable attribute | Tristan Gingold | 2022-09-30 | 2 | -5/+44 |
| * | synth: factorize code | Tristan Gingold | 2022-09-30 | 2 | -8/+9 |
| * | simul: create disconnections | Tristan Gingold | 2022-09-30 | 1 | -1/+42 |
| * | libraries.adb: do not set location of entity name of architecture. | Tristan Gingold | 2022-09-30 | 1 | -1/+0 |
| * | ortho/llvm6: handle llvm 15 (opaque pointers) | Tristan Gingold | 2022-09-29 | 1 | -39/+64 |
| * | simul: handle quiet attribute | Tristan Gingold | 2022-09-29 | 4 | -12/+88 |
| * | simul: factorize code, add sub_signal_type | Tristan Gingold | 2022-09-29 | 4 | -92/+73 |
| * | vhdl-canon: extract guard for signal assignment sensitivity | Tristan Gingold | 2022-09-29 | 1 | -1/+15 |
| * | simul: support guarded signal assignments (WIP) | Tristan Gingold | 2022-09-29 | 1 | -8/+79 |
| * | synth: handle guard signal in debugger | Tristan Gingold | 2022-09-28 | 3 | -57/+78 |
| * | simul: handle last_value attribute | Tristan Gingold | 2022-09-28 | 3 | -1/+31 |
| * | synth: handle guard signal in expressions | Tristan Gingold | 2022-09-28 | 2 | -0/+2 |
