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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-30 06:53:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-30 06:53:59 +0200 |
| commit | fe092cdc810cc559ed484f480d2072c43513a04a (patch) | |
| tree | 7e5b9067e46e6d6f40fb64601b44527cb640de17 /src | |
| parent | 3e23191c0ec808b588b11989b75985dc4ba1cfb1 (diff) | |
| download | ghdl-fe092cdc810cc559ed484f480d2072c43513a04a.tar.gz ghdl-fe092cdc810cc559ed484f480d2072c43513a04a.tar.bz2 ghdl-fe092cdc810cc559ed484f480d2072c43513a04a.zip | |
synth: factorize code
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 8 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 9 |
2 files changed, 9 insertions, 8 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 3eb3d2eed..0a07fc08b 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1034,6 +1034,14 @@ package body Simul.Vhdl_Simul is Ch := Synth_Expression (Inst, Get_Choice_Expression (Sw)); Eq := Is_Equal (Sel, Get_Memtyp (Ch)); end; + when Iir_Kind_Choice_By_Range => + declare + Bnd : Discrete_Range_Type; + begin + Elab.Vhdl_Types.Synth_Discrete_Range + (Inst, Get_Choice_Range (Sw), Bnd); + Eq := In_Range (Bnd, Read_Discrete (Sel)); + end; when Iir_Kind_Choice_By_Others => Eq := True; when others => diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index d53773ded..7b13214d2 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -1610,16 +1610,9 @@ package body Synth.Vhdl_Stmts is when Iir_Kind_Choice_By_Range => declare Bnd : Discrete_Range_Type; - Is_In : Boolean; begin Synth_Discrete_Range (Inst, Get_Choice_Range (Choice), Bnd); - case Bnd.Dir is - when Dir_To => - Is_In := Sel >= Bnd.Left and Sel <= Bnd.Right; - when Dir_Downto => - Is_In := Sel <= Bnd.Left and Sel >= Bnd.Right; - end case; - if Is_In then + if In_Range (Bnd, Sel) then return Stmts; end if; end; |