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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-01 18:19:26 +0200 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-01 18:19:26 +0200 | 
| commit | 842dc4a42232c559d0ff6c52b40fc40559c7fa30 (patch) | |
| tree | c7b48532bcf87392e086d1208db137656be13cd9 /src | |
| parent | 677d7c1971e3b35709eec2e802e7935cee02455d (diff) | |
| download | ghdl-842dc4a42232c559d0ff6c52b40fc40559c7fa30.tar.gz ghdl-842dc4a42232c559d0ff6c52b40fc40559c7fa30.tar.bz2 ghdl-842dc4a42232c559d0ff6c52b40fc40559c7fa30.zip | |
simul: finalize empty procedures
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 20 | 
1 files changed, 11 insertions, 9 deletions
| diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 64efe82fa..a17488fbf 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -803,16 +803,18 @@ package body Simul.Vhdl_Simul is              if Get_Suspend_Flag (Bod) then                 Next_Stmt := Get_Sequential_Statement_Chain (Bod); -               return; -               --  TODO: end of call. -            else -               Execute_Sequential_Statements (Process); -               Synth.Vhdl_Decls.Finalize_Declarations -                 (Sub_Inst, Get_Declaration_Chain (Bod), True); -               Synth_Subprogram_Back_Association -                 (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); -               Next_Stmt := Null_Node; +               if Next_Stmt /= Null_Node then +                  return; +               end if;              end if; + +            --  No suspension (or no statements). +            Execute_Sequential_Statements (Process); +            Synth.Vhdl_Decls.Finalize_Declarations +              (Sub_Inst, Get_Declaration_Chain (Bod), True); +            Synth_Subprogram_Back_Association +              (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); +            Next_Stmt := Null_Node;           end;        end if; | 
