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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-01 05:26:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-01 05:41:20 +0200 |
| commit | 2c755f301e995b73581c435d22a189ab874d5d84 (patch) | |
| tree | 366cbfc45e76ce42f8593cbff1b997bc52c5ff2b /src | |
| parent | d4dc28659c657f14aecd2e6b04d747f36e540bb2 (diff) | |
| download | ghdl-2c755f301e995b73581c435d22a189ab874d5d84.tar.gz ghdl-2c755f301e995b73581c435d22a189ab874d5d84.tar.bz2 ghdl-2c755f301e995b73581c435d22a189ab874d5d84.zip | |
simul: finalize declarations of procedure calls
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_decls.adb | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 92fcc920a..bee671e1b 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -523,6 +523,8 @@ package body Simul.Vhdl_Simul is -- Skip the resume statement. Stmt := Get_Chain (Stmt); pragma Assert (Get_Kind (Stmt) = Iir_Kind_Procedure_Call_Statement); + Synth.Vhdl_Decls.Finalize_Declarations + (Process.Instance, Get_Declaration_Chain (Bod), True); Synth_Subprogram_Back_Association (Process.Instance, Caller_Inst, Get_Interface_Declaration_Chain (Imp), @@ -806,6 +808,8 @@ package body Simul.Vhdl_Simul is -- TODO: end of call. else Execute_Sequential_Statements (Process); + Synth.Vhdl_Decls.Finalize_Declarations + (Sub_Inst, Get_Declaration_Chain (Bod), True); Synth_Subprogram_Back_Association (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Next_Stmt := Null_Node; diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index eb1d37e2f..0be74aeb6 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -878,6 +878,8 @@ package body Synth.Vhdl_Decls is null; when Iir_Kind_Use_Clause => null; + when Iir_Kind_Suspend_State_Declaration => + null; when others => Vhdl.Errors.Error_Kind ("finalize_declaration", Decl); end case; |