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* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
* synth: avoid extra conversion during alias elaborationTristan Gingold2022-10-141-6/+4
* simul: fix spurious error about multiple driversTristan Gingold2022-10-141-0/+2
* simul: handle delayed attributeTristan Gingold2022-10-142-6/+66
* synth: handle alias of access objects.Tristan Gingold2022-10-131-1/+1
* simul: handle last_event and last_activeTristan Gingold2022-10-133-4/+114
* elab-vhd_expr: handle more cases in exec_type_of_objectTristan Gingold2022-10-131-1/+4
* simul-vhdl_simul: keep default value of collapsed signalsTristan Gingold2022-10-131-1/+10
* simul-vhdl_elab: fix crash on association with implicit signalsTristan Gingold2022-10-131-1/+4
* simul: fix a crash due to missing strideTristan Gingold2022-10-131-5/+7
* synth-vhdl_stmts(synth_verification_unit): always set instance_pool.Tristan Gingold2022-10-131-1/+3
* synth: fix crashes on scalar attribute with anonymous subtype.Tristan Gingold2022-10-101-2/+2
* vhdl-canon: avoid a crash on optionnal condition. Fix #2212Tristan Gingold2022-10-101-1/+1
* simul: handle guarded concurrent assignmentsTristan Gingold2022-10-101-14/+32
* simul-vhdl_debug: handle state before elaborationTristan Gingold2022-10-101-0/+8
* vhdl-sem.adb(are_trees_equal): handle parenthesis expressions.Tristan Gingold2022-10-081-0/+4
* simul: signal attributes in actualsTristan Gingold2022-10-061-2/+4
* simul: complete concurrent procedure callsTristan Gingold2022-10-063-29/+43
* simul: fix initial value of record signalsTristan Gingold2022-10-061-2/+2
* simul: recompute object alias offsetsTristan Gingold2022-10-061-1/+14
* simul: fix signal attribute or guard as actual in connectionsTristan Gingold2022-10-062-11/+15
* simul: improve debugger (display of signals value)Tristan Gingold2022-10-064-38/+74
* simul: handle suspendable procedure call from sensitized process.Tristan Gingold2022-10-052-3/+11
* elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205Tristan Gingold2022-10-041-2/+4
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-033-17/+46
* translate, grt: add lib function for div and rem.Tristan Gingold2022-10-026-8/+148
* synth: improve error recoveryTristan Gingold2022-10-021-0/+3
* synth: detect division by 0, handle universal real/integer divisionTristan Gingold2022-10-021-3/+23
* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
* synth: avoid a crash on literal overflowTristan Gingold2022-10-011-1/+10
* synth: avoid on crash on overflow in rangesTristan Gingold2022-10-011-0/+8
* synth: improve handling of individual generic associationsTristan Gingold2022-10-011-17/+22
* simul: finalize empty proceduresTristan Gingold2022-10-011-9/+11
* simul: minor rewriteTristan Gingold2022-10-011-3/+2
* simul: finalize declarations of procedure callsTristan Gingold2022-10-012-0/+6
* synth: handle read for floatsTristan Gingold2022-09-302-8/+24
* synth: handle float-float conversionsTristan Gingold2022-09-301-3/+14
* simul: handle stable attributeTristan Gingold2022-09-302-5/+44
* synth: factorize codeTristan Gingold2022-09-302-8/+9
* simul: create disconnectionsTristan Gingold2022-09-301-1/+42
* libraries.adb: do not set location of entity name of architecture.Tristan Gingold2022-09-301-1/+0
* ortho/llvm6: handle llvm 15 (opaque pointers)Tristan Gingold2022-09-291-39/+64
* simul: handle quiet attributeTristan Gingold2022-09-294-12/+88
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-294-92/+73
* vhdl-canon: extract guard for signal assignment sensitivityTristan Gingold2022-09-291-1/+15
* simul: support guarded signal assignments (WIP)Tristan Gingold2022-09-291-8/+79
* synth: handle guard signal in debuggerTristan Gingold2022-09-283-57/+78
* simul: handle last_value attributeTristan Gingold2022-09-283-1/+31
* synth: handle guard signal in expressionsTristan Gingold2022-09-282-0/+2
* simul: fix handling of labels in next/exit statementsTristan Gingold2022-09-281-4/+13
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