testsuite/synth: rename arr02 to mem01

9 files changed, 277 insertions, 0 deletions

diff --git a/testsuite/synth/mem01/dpram1.vhdl b/testsuite/synth/mem01/dpram1.vhdl
new file mode 100644
index 000000000..ca1cf724a
--- /dev/null
+++ b/testsuite/synth/mem01/dpram1.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram1 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram1;
+
+architecture behav of dpram1 is
+  type memtype is array (15 downto 0) of std_logic_vector (7 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (to_integer(unsigned (raddr)));
+      mem (to_integer(unsigned (waddr))) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/dpram2.vhdl b/testsuite/synth/mem01/dpram2.vhdl
new file mode 100644
index 000000000..c21a0ee78
--- /dev/null
+++ b/testsuite/synth/mem01/dpram2.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram2 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram2;
+
+architecture behav of dpram2 is
+begin
+  process (clk)
+    type memtype is array (15 downto 0) of std_logic_vector (7 downto 0);
+    variable mem : memtype;
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (to_integer(unsigned (raddr)));
+      mem (to_integer(unsigned (waddr))) := wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/dpram3.vhdl b/testsuite/synth/mem01/dpram3.vhdl
new file mode 100644
index 000000000..a04478809
--- /dev/null
+++ b/testsuite/synth/mem01/dpram3.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram3 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram3;
+
+architecture behav of dpram3 is
+begin
+  process (clk)
+    type memtype is array (0 to 15) of std_logic_vector (7 downto 0);
+    variable mem : memtype;
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (to_integer(unsigned (raddr)));
+      mem (to_integer(unsigned (waddr))) := wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/rom1.vhdl b/testsuite/synth/mem01/rom1.vhdl
new file mode 100644
index 000000000..6b8245f30
--- /dev/null
+++ b/testsuite/synth/mem01/rom1.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity rom1 is
+  port (addr : std_logic_vector (3 downto 0);
+        val : out std_logic_vector (7 downto 0));
+end rom1;
+
+architecture behav of rom1 is
+  type t_myrom is array (0 to 15) of std_logic_vector (7 downto 0);
+  constant myrom : t_myrom :=
+    (x"00", x"01", x"02", x"03",
+     x"40", x"41", x"42", x"43",
+     x"f8", x"f9", x"fa", x"fb",
+     x"fc", x"fd", x"fe", x"ff");
+begin
+  val <= myrom (to_integer(unsigned(addr)));
+end behav;
diff --git a/testsuite/synth/mem01/tb_dpram1.vhdl b/testsuite/synth/mem01/tb_dpram1.vhdl
new file mode 100644
index 000000000..f7644fbfe
--- /dev/null
+++ b/testsuite/synth/mem01/tb_dpram1.vhdl
@@ -0,0 +1,40 @@
+entity tb_dpram1 is
+end tb_dpram1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram1 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram1
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= "0001";
+    wdat <= x"01";
+    pulse;
+
+    raddr <= "0001";
+    waddr <= "0010";
+    wdat <= x"02";
+    pulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/tb_dpram2.vhdl b/testsuite/synth/mem01/tb_dpram2.vhdl
new file mode 100644
index 000000000..f66363345
--- /dev/null
+++ b/testsuite/synth/mem01/tb_dpram2.vhdl
@@ -0,0 +1,40 @@
+entity tb_dpram2 is
+end tb_dpram2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram2 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram2
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= x"a";
+    wdat <= x"5a";
+    pulse;
+
+    raddr <= x"a";
+    waddr <= x"7";
+    wdat <= x"87";
+    pulse;
+    assert rdat = x"5a" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/tb_dpram3.vhdl b/testsuite/synth/mem01/tb_dpram3.vhdl
new file mode 100644
index 000000000..9cdbd8af7
--- /dev/null
+++ b/testsuite/synth/mem01/tb_dpram3.vhdl
@@ -0,0 +1,52 @@
+entity tb_dpram3 is
+end tb_dpram3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram3 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram3
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= x"a";
+    wdat <= x"5a";
+    pulse;
+
+    raddr <= x"a";
+    waddr <= x"7";
+    wdat <= x"87";
+    pulse;
+    assert rdat = x"5a" severity failure;
+
+    raddr <= x"7";
+    waddr <= x"1";
+    wdat <= x"e1";
+    pulse;
+    assert rdat = x"87" severity failure;
+
+    raddr <= x"1";
+    waddr <= x"3";
+    wdat <= x"c3";
+    pulse;
+    assert rdat = x"e1" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/tb_rom1.vhdl b/testsuite/synth/mem01/tb_rom1.vhdl
new file mode 100644
index 000000000..4a7f96d29
--- /dev/null
+++ b/testsuite/synth/mem01/tb_rom1.vhdl
@@ -0,0 +1,38 @@
+entity tb_rom1 is
+end tb_rom1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_rom1 is
+  signal addr : std_logic_vector(3 downto 0);
+  signal dat : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.rom1
+    port map (addr, dat);
+
+  process
+  begin
+    addr <= "0000";
+    wait for 1 ns;
+    assert dat = x"00" severity failure;
+    
+    addr <= "0101";
+    wait for 1 ns;
+    assert dat = x"41" severity failure;
+    
+    addr <= "1100";
+    wait for 1 ns;
+    assert dat = x"fc" severity failure;
+    
+    addr <= "1011";
+    wait for 1 ns;
+    assert dat = x"fb" severity failure;
+    
+    addr <= "0010";
+    wait for 1 ns;
+    assert dat = x"02" severity failure;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh
new file mode 100755
index 000000000..8d0b840a5
--- /dev/null
+++ b/testsuite/synth/mem01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in rom1 dpram1 dpram2 dpram3; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"