testsuite/synth: add tests for #1175

4 files changed, 51 insertions, 0 deletions

diff --git a/testsuite/synth/issue1175/issue.vhdl b/testsuite/synth/issue1175/issue.vhdl
new file mode 100644
index 000000000..f729452c7
--- /dev/null
+++ b/testsuite/synth/issue1175/issue.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity issue is
+    port (foo  : in  std_logic_vector(32-1 downto 0);
+          bar  : out std_logic);
+end issue;
+
+architecture rtl of issue is
+        alias a_bar is foo(foo'high);
+begin
+    bar <= a_bar;
+end architecture;
diff --git a/testsuite/synth/issue1175/issue2.vhdl b/testsuite/synth/issue1175/issue2.vhdl
new file mode 100644
index 000000000..9808a857a
--- /dev/null
+++ b/testsuite/synth/issue1175/issue2.vhdl
@@ -0,0 +1,10 @@
+entity issue2 is
+    port (foo  : in  bit_vector(32-1 downto 0);
+          bar  : out bit);
+end issue2;
+
+architecture rtl of issue2 is
+        alias a_bar is foo(foo'high);
+begin
+    bar <= a_bar;
+end architecture;
diff --git a/testsuite/synth/issue1175/issue3.vhdl b/testsuite/synth/issue1175/issue3.vhdl
new file mode 100644
index 000000000..c7fb4a750
--- /dev/null
+++ b/testsuite/synth/issue1175/issue3.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue3 is
+    port (foo  : in  std_logic_vector(32-1 downto 0);
+          bar  : out std_logic);
+end issue3;
+
+architecture rtl of issue3 is
+        alias a_bar is foo(foo'high);
+begin
+    bar <= a_bar;
+end architecture;
diff --git a/testsuite/synth/issue1175/testsuite.sh b/testsuite/synth/issue1175/testsuite.sh
new file mode 100755
index 000000000..5c008e877
--- /dev/null
+++ b/testsuite/synth/issue1175/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze issue
+clean
+
+GHDL_STD_FLAGS=--std=08
+synth_analyze issue
+synth_analyze issue2
+synth_analyze issue3
+clean
+
+echo "Test successful"