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authorTristan Gingold <tgingold@free.fr>2020-03-29 08:29:17 +0200
committerTristan Gingold <tgingold@free.fr>2020-03-29 08:29:17 +0200
commit9f6ac61e196ccf49960bbdb2e7d71cdd96ddd10d (patch)
tree52c8103df73a69b209c354321ffd90540c966fc6 /testsuite/synth/issue1175/issue3.vhdl
parent6739ef05016a6148f899be092a4e9bb4512d0d78 (diff)
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testsuite/synth: add tests for #1175
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diff --git a/testsuite/synth/issue1175/issue3.vhdl b/testsuite/synth/issue1175/issue3.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue3 is
+ port (foo : in std_logic_vector(32-1 downto 0);
+ bar : out std_logic);
+end issue3;
+
+architecture rtl of issue3 is
+ alias a_bar is foo(foo'high);
+begin
+ bar <= a_bar;
+end architecture;