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author | Tristan Gingold <tgingold@free.fr> | 2020-03-29 08:29:17 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-29 08:29:17 +0200 |
commit | 9f6ac61e196ccf49960bbdb2e7d71cdd96ddd10d (patch) | |
tree | 52c8103df73a69b209c354321ffd90540c966fc6 /testsuite/synth/issue1175/issue3.vhdl | |
parent | 6739ef05016a6148f899be092a4e9bb4512d0d78 (diff) | |
download | ghdl-9f6ac61e196ccf49960bbdb2e7d71cdd96ddd10d.tar.gz ghdl-9f6ac61e196ccf49960bbdb2e7d71cdd96ddd10d.tar.bz2 ghdl-9f6ac61e196ccf49960bbdb2e7d71cdd96ddd10d.zip |
testsuite/synth: add tests for #1175
Diffstat (limited to 'testsuite/synth/issue1175/issue3.vhdl')
-rw-r--r-- | testsuite/synth/issue1175/issue3.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/issue1175/issue3.vhdl b/testsuite/synth/issue1175/issue3.vhdl new file mode 100644 index 000000000..c7fb4a750 --- /dev/null +++ b/testsuite/synth/issue1175/issue3.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity issue3 is + port (foo : in std_logic_vector(32-1 downto 0); + bar : out std_logic); +end issue3; + +architecture rtl of issue3 is + alias a_bar is foo(foo'high); +begin + bar <= a_bar; +end architecture; |