synth: add a test for concatenation.

1 files changed, 12 insertions, 0 deletions

diff --git a/testsuite/synth/concat01/concat01.vhdl b/testsuite/synth/concat01/concat01.vhdl
new file mode 100644
index 000000000..3fe968616
--- /dev/null
+++ b/testsuite/synth/concat01/concat01.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity concat01 is
+  port (a, b : in std_logic;
+        z : out std_logic_vector(1 downto 0));
+end concat01;
+
+architecture behav of concat01 is
+begin
+  z <= a & b;
+end behav;