From 7f0a70e0d4777a2b9c29d6b17f2385d2d3bc1ced Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 19 Jul 2019 06:41:39 +0200
Subject: synth: add a test for concatenation.

---
 testsuite/synth/concat01/concat01.vhdl | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 testsuite/synth/concat01/concat01.vhdl

(limited to 'testsuite/synth/concat01/concat01.vhdl')

diff --git a/testsuite/synth/concat01/concat01.vhdl b/testsuite/synth/concat01/concat01.vhdl
new file mode 100644
index 000000000..3fe968616
--- /dev/null
+++ b/testsuite/synth/concat01/concat01.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity concat01 is
+  port (a, b : in std_logic;
+        z : out std_logic_vector(1 downto 0));
+end concat01;
+
+architecture behav of concat01 is
+begin
+  z <= a & b;
+end behav;
-- 
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