testsuite/synth/concat01/concat01.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity concat01 is
  port (a, b : in std_logic;
        z : out std_logic_vector(1 downto 0));
end concat01;

architecture behav of concat01 is
begin
  z <= a & b;
end behav;