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authorTristan Gingold <tgingold@free.fr>2019-07-19 06:41:39 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-19 06:50:53 +0200
commit7f0a70e0d4777a2b9c29d6b17f2385d2d3bc1ced (patch)
treef12c13d6a1027815e6f0a2a778801c67b8116935 /testsuite
parent94912cf6e8862c9f5fe88f1e5314d4699f8e5659 (diff)
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synth: add a test for concatenation.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/concat01/concat01.vhdl12
-rw-r--r--testsuite/synth/concat01/tb_concat01.vhdl34
-rwxr-xr-xtestsuite/synth/concat01/testsuite.sh16
3 files changed, 62 insertions, 0 deletions
diff --git a/testsuite/synth/concat01/concat01.vhdl b/testsuite/synth/concat01/concat01.vhdl
new file mode 100644
index 000000000..3fe968616
--- /dev/null
+++ b/testsuite/synth/concat01/concat01.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity concat01 is
+ port (a, b : in std_logic;
+ z : out std_logic_vector(1 downto 0));
+end concat01;
+
+architecture behav of concat01 is
+begin
+ z <= a & b;
+end behav;
diff --git a/testsuite/synth/concat01/tb_concat01.vhdl b/testsuite/synth/concat01/tb_concat01.vhdl
new file mode 100644
index 000000000..2709328f0
--- /dev/null
+++ b/testsuite/synth/concat01/tb_concat01.vhdl
@@ -0,0 +1,34 @@
+entity tb_concat01 is
+end tb_concat01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_concat01 is
+ signal a : std_logic;
+ signal b : std_logic;
+ signal z : std_logic_vector(1 downto 0);
+begin
+ dut: entity work.concat01
+ port map (a, b, z);
+
+ process
+ begin
+ a <= '0';
+ b <= '1';
+ wait for 1 ns;
+ assert z = "01" severity failure;
+
+ a <= '1';
+ b <= '1';
+ wait for 1 ns;
+ assert z = "11" severity failure;
+
+ a <= '1';
+ b <= '0';
+ wait for 1 ns;
+ assert z = "10" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/concat01/testsuite.sh b/testsuite/synth/concat01/testsuite.sh
new file mode 100755
index 000000000..083547e63
--- /dev/null
+++ b/testsuite/synth/concat01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in concat01; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+done
+
+echo "Test successful"