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authorTristan Gingold <tgingold@free.fr>2023-02-08 16:51:19 +0100
committerTristan Gingold <tgingold@free.fr>2023-02-08 16:51:19 +0100
commit5c18960e811ace9ad7418e452c4d5c802ad30e2f (patch)
tree6059f42cebf652808c85eec46c74bdaf43321d09
parentb0bfbef2ef699e5b2823f9a4941b8690628b9b7a (diff)
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simul: improve support of PSL endpoints
-rw-r--r--src/simul/simul-vhdl_simul.adb9
-rw-r--r--src/synth/elab-vhdl_stmts.adb13
2 files changed, 12 insertions, 10 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index d93d13869..e898031bf 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2245,14 +2245,7 @@ package body Simul.Vhdl_Simul is
-- TODO
null;
when Iir_Kind_Psl_Endpoint_Declaration =>
- declare
- Val : Valtyp;
- begin
- Val := Create_Value_Memory (Bit_Type, Global_Pool'Access);
- Write_Discrete (Val, 0);
- -- TODO: create the object/signal during elaboration
- Create_Object (Proc.Instance, Proc.Proc, Val);
- end;
+ null;
when others =>
null;
end case;
diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb
index ebb2380b2..79ef52d26 100644
--- a/src/synth/elab-vhdl_stmts.adb
+++ b/src/synth/elab-vhdl_stmts.adb
@@ -281,9 +281,18 @@ package body Elab.Vhdl_Stmts is
| Iir_Kind_Psl_Assume_Directive
| Iir_Kind_Psl_Assert_Directive
| Iir_Kind_Psl_Cover_Directive
- | Iir_Kind_Psl_Declaration
- | Iir_Kind_Psl_Endpoint_Declaration =>
+ | Iir_Kind_Psl_Declaration =>
null;
+ when Iir_Kind_Psl_Endpoint_Declaration =>
+ declare
+ Val : Valtyp;
+ begin
+ Val := Create_Value_Memory
+ (Boolean_Type, Global_Pool'Access);
+ Write_Discrete (Val, 0);
+ Create_Object (Syn_Inst, Stmt, Val);
+ end;
+
when Iir_Kind_Component_Instantiation_Statement =>
if Is_Component_Instantiation (Stmt) then
Elab_Component_Instantiation_Statement (Syn_Inst, Stmt);