Dependency Graphs (#2308)

* Further fixes to the example code.

* Bumped dependencies.

* Fixed Debouncer example code.

* Some more cleanup.

* Black's opinion.

* Run with pyVHDLModel dev-branch.

* Fixed imports for Name.

* Fixed test case.

* Added a formatter to write dependency graphs and hierarchy as graphml.

* Improved GraphML formatting.

* Write compile order graph.

* Computing compile order.

* Bumped dependencies.

* Black's opinion.

* Fixed incorrect dependency.

34 files changed, 698 insertions, 338 deletions

diff --git a/doc/requirements.txt b/doc/requirements.txt
index b40787cd7..c787fab4f 100644
--- a/doc/requirements.txt
+++ b/doc/requirements.txt
@@ -8,11 +8,11 @@ python-dateutil>=2.8.2
 # sphinxcontrib-textstyle>=0.2.1
 # sphinxcontrib-spelling>=2.2.0
 # changelog>=0.3.5
-autoapi
+autoapi>=2.0.1
 sphinx_fontawesome>=0.0.6
 sphinx_autodoc_typehints>=1.19.5
 
 # BuildTheDocs Extensions (mostly patched Sphinx extensions)
-btd.sphinx.autoprogram>=0.1.6.post1
+btd.sphinx.autoprogram>=0.1.7.post1
 btd.sphinx.graphviz>=2.3.1.post1
 btd.sphinx.inheritance_diagram>=2.3.1.post1
diff --git a/pyGHDL/cli/requirements.txt b/pyGHDL/cli/requirements.txt
index e453bcbde..063ef74f6 100644
--- a/pyGHDL/cli/requirements.txt
+++ b/pyGHDL/cli/requirements.txt
@@ -1,5 +1,5 @@
 -r ../dom/requirements.txt
 
-pyTooling>=2.1.0
+pyTooling>=2.11.0
 pyTooling.TerminalUI>=1.5.9
 pyAttributes>=2.3.2
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index a1fe40866..968d3afc9 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -41,15 +41,14 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 """
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    SimpleAggregateElement as VHDLModel_SimpleAggregateElement,
-    IndexedAggregateElement as VHDLModel_IndexedAggregateElement,
-    RangedAggregateElement as VHDLModel_RangedAggregateElement,
-    NamedAggregateElement as VHDLModel_NamedAggregateElement,
-    OthersAggregateElement as VHDLModel_OthersAggregateElement,
-    ExpressionUnion,
-    Symbol,
-)
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Expression import SimpleAggregateElement as VHDLModel_SimpleAggregateElement
+from pyVHDLModel.Expression import IndexedAggregateElement as VHDLModel_IndexedAggregateElement
+from pyVHDLModel.Expression import RangedAggregateElement as VHDLModel_RangedAggregateElement
+from pyVHDLModel.Expression import NamedAggregateElement as VHDLModel_NamedAggregateElement
+from pyVHDLModel.Expression import OthersAggregateElement as VHDLModel_OthersAggregateElement
+
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom.Range import Range
diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py
index e43ea173e..7133c86a2 100644
--- a/pyGHDL/dom/Attribute.py
+++ b/pyGHDL/dom/Attribute.py
@@ -34,13 +34,11 @@ from typing import List
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    Attribute as VHDLModel_Attribute,
-    AttributeSpecification as VHDLModel_AttributeSpecification,
-    Name,
-    SubtypeOrSymbol,
-    EntityClass,
-)
+from pyVHDLModel.Name import Name
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Declaration import EntityClass, Attribute as VHDLModel_Attribute
+from pyVHDLModel.Declaration import AttributeSpecification as VHDLModel_AttributeSpecification
+
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
@@ -54,7 +52,7 @@ from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
 
 @export
 class Attribute(VHDLModel_Attribute, DOMMixin):
-    def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol, documentation: str = None):
+    def __init__(self, node: Iir, identifier: str, subtype: Symbol, documentation: str = None):
         super().__init__(identifier, subtype, documentation)
         DOMMixin.__init__(self, node)
 
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py
index 8dcec9bdb..3b3c06f2e 100644
--- a/pyGHDL/dom/Concurrent.py
+++ b/pyGHDL/dom/Concurrent.py
@@ -34,43 +34,37 @@ from typing import Iterable
 
 from pyTooling.Decorators import export
 
-from pyGHDL.dom.Range import Range
-from pyGHDL.dom.Symbol import (
-    ArchitectureSymbol,
-    EntityInstantiationSymbol,
-    ComponentInstantiationSymbol,
-    ConfigurationInstantiationSymbol,
-)
-from pyVHDLModel.SyntaxModel import (
+from pyVHDLModel.Base import ExpressionUnion, WaveformElement as VHDLModel_WaveformElement
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Association import (
+    AssociationItem,
     GenericAssociationItem as VHDLModel_GenericAssociationItem,
     PortAssociationItem as VHDLModel_PortAssociationItem,
     ParameterAssociationItem as VHDLModel_ParameterAssociationItem,
+)
+from pyVHDLModel.Sequential import SequentialStatement
+from pyVHDLModel.Concurrent import (
     ComponentInstantiation as VHDLModel_ComponentInstantiation,
     EntityInstantiation as VHDLModel_EntityInstantiation,
     ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation,
-    ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement,
     ProcessStatement as VHDLModel_ProcessStatement,
+    ConcurrentProcedureCall as VHDLModel_ConcurrentProcedureCall,
+    ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement,
     IfGenerateBranch as VHDLModel_IfGenerateBranch,
     ElsifGenerateBranch as VHDLModel_ElsifGenerateBranch,
     ElseGenerateBranch as VHDLModel_ElseGenerateBranch,
     IfGenerateStatement as VHDLModel_IfGenerateStatement,
-    IndexedGenerateChoice as VHDLModel_IndexedGenerateChoice,
-    RangedGenerateChoice as VHDLModel_RangedGenerateChoice,
-    OthersGenerateCase as VHDLModel_OthersGenerateCase,
-    GenerateCase as VHDLModel_GenerateCase,
+    ConcurrentChoice,
+    ConcurrentCase,
     CaseGenerateStatement as VHDLModel_CaseGenerateStatement,
     ForGenerateStatement as VHDLModel_ForGenerateStatement,
-    WaveformElement as VHDLModel_WaveformElement,
     ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment,
-    ConcurrentProcedureCall as VHDLModel_ConcurrentProcedureCall,
     ConcurrentAssertStatement as VHDLModel_ConcurrentAssertStatement,
-    Name,
     ConcurrentStatement,
-    SequentialStatement,
-    ExpressionUnion,
-    ConcurrentChoice,
-    ConcurrentCase,
-    AssociationItem,
+    GenerateCase as VHDLModel_GenerateCase,
+    OthersGenerateCase as VHDLModel_OthersGenerateCase,
+    IndexedGenerateChoice as VHDLModel_IndexedGenerateChoice,
+    RangedGenerateChoice as VHDLModel_RangedGenerateChoice,
 )
 
 from pyGHDL.libghdl import Iir, utils
@@ -82,25 +76,32 @@ from pyGHDL.dom._Utils import (
     GetComponentInstantiationSymbol,
     GetConfigurationInstantiationSymbol,
 )
+from pyGHDL.dom.Range import Range
+from pyGHDL.dom.Symbol import (
+    ArchitectureSymbol,
+    EntityInstantiationSymbol,
+    ComponentInstantiationSymbol,
+    ConfigurationInstantiationSymbol,
+)
 
 
 @export
 class GenericAssociationItem(VHDLModel_GenericAssociationItem, DOMMixin):
-    def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None):
+    def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Symbol = None):
         super().__init__(actual, formal)
         DOMMixin.__init__(self, associationNode)
 
 
 @export
 class PortAssociationItem(VHDLModel_PortAssociationItem, DOMMixin):
-    def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None):
+    def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Symbol = None):
         super().__init__(actual, formal)
         DOMMixin.__init__(self, associationNode)
 
 
 @export
 class ParameterAssociationItem(VHDLModel_ParameterAssociationItem, DOMMixin):
-    def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None):
+    def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Symbol = None):
         super().__init__(actual, formal)
         DOMMixin.__init__(self, associationNode)
 
@@ -222,7 +223,7 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin):
         label: str = None,
         declaredItems: Iterable = None,
         statements: Iterable[SequentialStatement] = None,
-        sensitivityList: Iterable[Name] = None,
+        sensitivityList: Iterable[Symbol] = None,
     ):
         super().__init__(label, declaredItems, statements, sensitivityList)
         DOMMixin.__init__(self, processNode)
@@ -642,7 +643,7 @@ class ConcurrentSimpleSignalAssignment(VHDLModel_ConcurrentSimpleSignalAssignmen
         self,
         assignmentNode: Iir,
         label: str,
-        target: Name,
+        target: Symbol,
         waveform: Iterable[WaveformElement],
     ):
         super().__init__(label, target, waveform)
@@ -668,7 +669,7 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin):
         self,
         callNode: Iir,
         label: str,
-        procedureName: Name,
+        procedureName: Symbol,
         parameterMappings: Iterable,
     ):
         super().__init__(label, procedureName, parameterMappings)
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index 881a7f2eb..079364742 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -39,56 +39,46 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 
 
 """
-from typing import Iterable, Union
+from typing import Iterable
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel import (
-    ContextUnion as VHDLModel_ContextUnion,
-    LibraryClause as VHDLModel_LibraryClause,
-    UseClause as VHDLModel_UseClause,
-    ContextReference as VHDLModel_ContextReference,
-    Name,
-    ContextUnion,
-)
-from pyVHDLModel.SyntaxModel import (
-    Entity as VHDLModel_Entity,
-    Architecture as VHDLModel_Architecture,
-    Package as VHDLModel_Package,
-    PackageBody as VHDLModel_PackageBody,
-    PackageInstantiation as VHDLModel_PackageInstantiation,
-    Context as VHDLModel_Context,
-    Configuration as VHDLModel_Configuration,
-    Component as VHDLModel_Component,
-    GenericInterfaceItem,
-    PortInterfaceItem,
-    ConcurrentStatement,
-)
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Instantiation import PackageInstantiation as VHDLModel_PackageInstantiation
+from pyVHDLModel.Interface import GenericInterfaceItem, PortInterfaceItem
+from pyVHDLModel.Concurrent import ConcurrentStatement
+from pyVHDLModel.DesignUnit import Context as VHDLModel_Context
+from pyVHDLModel.DesignUnit import Package as VHDLModel_Package
+from pyVHDLModel.DesignUnit import PackageBody as VHDLModel_PackageBody
+from pyVHDLModel.DesignUnit import Entity as VHDLModel_Entity
+from pyVHDLModel.DesignUnit import Architecture as VHDLModel_Architecture
+from pyVHDLModel.DesignUnit import Component as VHDLModel_Component
+from pyVHDLModel.DesignUnit import Configuration as VHDLModel_Configuration
+from pyVHDLModel.DesignUnit import LibraryClause as VHDLModel_LibraryClause
+from pyVHDLModel.DesignUnit import UseClause as VHDLModel_UseClause
+from pyVHDLModel.DesignUnit import ContextReference as VHDLModel_ContextReference
+from pyVHDLModel.DesignUnit import ContextUnion as VHDLModel_ContextUnion
 
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin, Position, DOMException
 from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol, GetContextSymbol
-from pyGHDL.dom._Translate import (
-    GetGenericsFromChainedNodes,
-    GetPortsFromChainedNodes,
-    GetDeclaredItemsFromChainedNodes,
-    GetConcurrentStatementsFromChainedNodes,
-)
+from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes
+from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes
 from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol
 
 
 @export
 class LibraryClause(VHDLModel_LibraryClause, DOMMixin):
-    def __init__(self, libraryNode: Iir, symbols: Iterable[Name]):
+    def __init__(self, libraryNode: Iir, symbols: Iterable[Symbol]):
         super().__init__(symbols)
         DOMMixin.__init__(self, libraryNode)
 
 
 @export
 class UseClause(VHDLModel_UseClause, DOMMixin):
-    def __init__(self, useNode: Iir, symbols: Iterable[Name]):
+    def __init__(self, useNode: Iir, symbols: Iterable[Symbol]):
         super().__init__(symbols)
         DOMMixin.__init__(self, useNode)
 
@@ -103,7 +93,7 @@ class UseClause(VHDLModel_UseClause, DOMMixin):
 
 @export
 class ContextReference(VHDLModel_ContextReference, DOMMixin):
-    def __init__(self, contextNode: Iir, symbols: Iterable[Name]):
+    def __init__(self, contextNode: Iir, symbols: Iterable[Symbol]):
         super().__init__(symbols)
         DOMMixin.__init__(self, contextNode)
 
@@ -269,7 +259,7 @@ class PackageInstantiation(VHDLModel_PackageInstantiation, DOMMixin):
         self,
         node: Iir,
         identifier: str,
-        uninstantiatedPackageName: Name,
+        uninstantiatedPackageName: Symbol,
         #        genericItems: List[GenericInterfaceItem] = None,
         documentation: str = None,
     ):
@@ -296,7 +286,7 @@ class Context(VHDLModel_Context, DOMMixin):
         self,
         node: Iir,
         identifier: str,
-        references: Iterable[ContextUnion] = None,
+        references: Iterable[VHDLModel_ContextUnion] = None,
         documentation: str = None,
     ):
         super().__init__(identifier, references, documentation)
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 81ecfa380..608801af6 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -34,17 +34,17 @@ from typing import List, Union
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Expression import (
     UnaryExpression as VHDLModel_UnaryExpression,
-    BinaryExpression as VHDLModel_BinaryExpression,
-    InverseExpression as VHDLModel_InverseExpression,
-    IdentityExpression as VHDLModel_IdentityExpression,
     NegationExpression as VHDLModel_NegationExpression,
+    IdentityExpression as VHDLModel_IdentityExpression,
+    InverseExpression as VHDLModel_InverseExpression,
     AbsoluteExpression as VHDLModel_AbsoluteExpression,
-    SubExpression as VHDLModel_ParenthesisExpression,
     TypeConversion as VHDLModel_TypeConversion,
-    FunctionCall as VHDLModel_FunctionCall,
-    QualifiedExpression as VHDLModel_QualifiedExpression,
+    SubExpression as VHDLModel_ParenthesisExpression,
+    BinaryExpression as VHDLModel_BinaryExpression,
     RangeExpression as VHDLModel_RangeExpression,
     AscendingRangeExpression as VHDLModel_AscendingRangeExpression,
     DescendingRangeExpression as VHDLModel_DescendingRangeExpression,
@@ -64,29 +64,28 @@ from pyVHDLModel.SyntaxModel import (
     XnorExpression as VHDLModel_XnorExpression,
     EqualExpression as VHDLModel_EqualExpression,
     UnequalExpression as VHDLModel_UnequalExpression,
-    LessThanExpression as VHDLModel_LessThanExpression,
-    LessEqualExpression as VHDLModel_LessEqualExpression,
     GreaterThanExpression as VHDLModel_GreaterThanExpression,
     GreaterEqualExpression as VHDLModel_GreaterEqualExpression,
+    LessThanExpression as VHDLModel_LessThanExpression,
+    LessEqualExpression as VHDLModel_LessEqualExpression,
     MatchingEqualExpression as VHDLModel_MatchingEqualExpression,
     MatchingUnequalExpression as VHDLModel_MatchingUnequalExpression,
-    MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression,
-    MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression,
     MatchingGreaterThanExpression as VHDLModel_MatchingGreaterThanExpression,
     MatchingGreaterEqualExpression as VHDLModel_MatchingGreaterEqualExpression,
+    MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression,
+    MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression,
     ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression,
     ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression,
     ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression,
     ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression,
     RotateRightExpression as VHDLModel_RotateRightExpression,
     RotateLeftExpression as VHDLModel_RotateLeftExpression,
+    QualifiedExpression as VHDLModel_QualifiedExpression,
+    FunctionCall as VHDLModel_FunctionCall,
     SubtypeAllocation as VHDLModel_SubtypeAllocation,
     QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation,
-    Aggregate as VHDLModel_Aggregate,
-    ExpressionUnion,
     AggregateElement,
-    SubtypeOrSymbol,
-    Symbol,
+    Aggregate as VHDLModel_Aggregate,
 )
 
 from pyGHDL.libghdl import utils
@@ -434,7 +433,7 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinar
 
 @export
 class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin):
-    def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: ExpressionUnion):
+    def __init__(self, node: Iir, subtype: Symbol, operand: ExpressionUnion):
         super().__init__(subtype, operand)
         DOMMixin.__init__(self, node)
 
diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py
index 44b67a79c..25128772f 100644
--- a/pyGHDL/dom/InterfaceItem.py
+++ b/pyGHDL/dom/InterfaceItem.py
@@ -34,21 +34,18 @@ from typing import List, Iterable
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem,
-    GenericTypeInterfaceItem as VHDLModel_GenericTypeInterfaceItem,
-    GenericPackageInterfaceItem as VHDLModel_GenericPackageInterfaceItem,
-    GenericProcedureInterfaceItem as VHDLModel_GenericProcedureInterfaceItem,
-    GenericFunctionInterfaceItem as VHDLModel_GenericFunctionInterfaceItem,
-    PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem,
-    ParameterConstantInterfaceItem as VHDLModel_ParameterConstantInterfaceItem,
-    ParameterVariableInterfaceItem as VHDLModel_ParameterVariableInterfaceItem,
-    ParameterSignalInterfaceItem as VHDLModel_ParameterSignalInterfaceItem,
-    ParameterFileInterfaceItem as VHDLModel_ParameterFileInterfaceItem,
-    Mode,
-    SubtypeOrSymbol,
-    ExpressionUnion,
-)
+from pyVHDLModel.Base import Mode, ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Interface import GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem
+from pyVHDLModel.Interface import GenericTypeInterfaceItem as VHDLModel_GenericTypeInterfaceItem
+from pyVHDLModel.Interface import GenericProcedureInterfaceItem as VHDLModel_GenericProcedureInterfaceItem
+from pyVHDLModel.Interface import GenericFunctionInterfaceItem as VHDLModel_GenericFunctionInterfaceItem
+from pyVHDLModel.Interface import GenericPackageInterfaceItem as VHDLModel_GenericPackageInterfaceItem
+from pyVHDLModel.Interface import PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem
+from pyVHDLModel.Interface import ParameterConstantInterfaceItem as VHDLModel_ParameterConstantInterfaceItem
+from pyVHDLModel.Interface import ParameterVariableInterfaceItem as VHDLModel_ParameterVariableInterfaceItem
+from pyVHDLModel.Interface import ParameterSignalInterfaceItem as VHDLModel_ParameterSignalInterfaceItem
+from pyVHDLModel.Interface import ParameterFileInterfaceItem as VHDLModel_ParameterFileInterfaceItem
 
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
@@ -64,7 +61,7 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi
         node: Iir,
         identifiers: List[str],
         mode: Mode,
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion,
         documentation: str = None,
     ):
@@ -149,7 +146,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin):
         node: Iir,
         identifiers: List[str],
         mode: Mode,
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion = None,
         documentation: str = None,
     ):
@@ -179,7 +176,7 @@ class ParameterConstantInterfaceItem(VHDLModel_ParameterConstantInterfaceItem, D
         node: Iir,
         identifiers: List[str],
         mode: Mode,
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion = None,
         documentation: str = None,
     ):
@@ -209,7 +206,7 @@ class ParameterVariableInterfaceItem(VHDLModel_ParameterVariableInterfaceItem, D
         node: Iir,
         identifiers: List[str],
         mode: Mode,
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion = None,
         documentation: str = None,
     ):
@@ -239,7 +236,7 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi
         node: Iir,
         identifiers: List[str],
         mode: Mode,
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion = None,
         documentation: str = None,
     ):
@@ -264,7 +261,7 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi
 
 @export
 class ParameterFileInterfaceItem(VHDLModel_ParameterFileInterfaceItem, DOMMixin):
-    def __init__(self, node: Iir, identifiers: List[str], subtype: SubtypeOrSymbol, documentation: str = None):
+    def __init__(self, node: Iir, identifiers: List[str], subtype: Symbol, documentation: str = None):
         super().__init__(identifiers, subtype, documentation)
         DOMMixin.__init__(self, node)
 
diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index e8a87bc19..d90fccf40 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -32,16 +32,15 @@
 # ============================================================================
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    NullLiteral as VHDLModel_NullLiteral,
-    EnumerationLiteral as VHDLModel_EnumerationLiteral,
-    IntegerLiteral as VHDLModel_IntegerLiteral,
-    FloatingPointLiteral as VHDLModel_FloatingPointLiteral,
-    PhysicalIntegerLiteral as VHDLModel_PhysicalIntegerLiteral,
-    PhysicalFloatingLiteral as VHDLModel_PhysicalFloatingLiteral,
-    CharacterLiteral as VHDLModel_CharacterLiteral,
-    StringLiteral as VHDLModel_StringLiteral,
-)
+from pyVHDLModel.Expression import NullLiteral as VHDLModel_NullLiteral
+from pyVHDLModel.Expression import EnumerationLiteral as VHDLModel_EnumerationLiteral
+from pyVHDLModel.Expression import IntegerLiteral as VHDLModel_IntegerLiteral
+from pyVHDLModel.Expression import FloatingPointLiteral as VHDLModel_FloatingPointLiteral
+from pyVHDLModel.Expression import PhysicalIntegerLiteral as VHDLModel_PhysicalIntegerLiteral
+from pyVHDLModel.Expression import PhysicalFloatingLiteral as VHDLModel_PhysicalFloatingLiteral
+from pyVHDLModel.Expression import CharacterLiteral as VHDLModel_CharacterLiteral
+from pyVHDLModel.Expression import StringLiteral as VHDLModel_StringLiteral
+
 from pyGHDL.libghdl import name_table, str_table
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py
index 71860f676..d613dd24c 100644
--- a/pyGHDL/dom/Misc.py
+++ b/pyGHDL/dom/Misc.py
@@ -37,9 +37,8 @@
 """
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    Alias as VHDLModel_Alias,
-)
+from pyVHDLModel.Declaration import Alias as VHDLModel_Alias
+
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode
diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py
index c66d20661..5e0bdd7de 100644
--- a/pyGHDL/dom/Names.py
+++ b/pyGHDL/dom/Names.py
@@ -34,17 +34,16 @@ from typing import List
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    SimpleName as VHDLModel_SimpleName,
-    ParenthesisName as VHDLModel_ParenthesisName,
-    IndexedName as VHDLModel_IndexedName,
-    SlicedName as VHDLModel_SlicedName,
-    SelectedName as VHDLModel_SelectedName,
-    AttributeName as VHDLModel_AttributeName,
-    AllName as VHDLModel_AllName,
-    OpenName as VHDLModel_OpenName,
-    Name,
-)
+from pyVHDLModel.Name import Name
+from pyVHDLModel.Name import SimpleName as VHDLModel_SimpleName
+from pyVHDLModel.Name import ParenthesisName as VHDLModel_ParenthesisName
+from pyVHDLModel.Name import IndexedName as VHDLModel_IndexedName
+from pyVHDLModel.Name import SlicedName as VHDLModel_SlicedName
+from pyVHDLModel.Name import SelectedName as VHDLModel_SelectedName
+from pyVHDLModel.Name import AttributeName as VHDLModel_AttributeName
+from pyVHDLModel.Name import AllName as VHDLModel_AllName
+from pyVHDLModel.Name import OpenName as VHDLModel_OpenName
+
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 
diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py
index e0b837c57..e84396433 100644
--- a/pyGHDL/dom/NonStandard.py
+++ b/pyGHDL/dom/NonStandard.py
@@ -42,13 +42,10 @@ from typing import Any
 
 from pyTooling.Decorators import export
 
-from pyGHDL.dom.Names import SimpleName
 from pyVHDLModel import VHDLVersion
-from pyVHDLModel.SyntaxModel import (
-    Design as VHDLModel_Design,
-    Library as VHDLModel_Library,
-    Document as VHDLModel_Document,
-)
+from pyVHDLModel import Design as VHDLModel_Design
+from pyVHDLModel import Library as VHDLModel_Library
+from pyVHDLModel import Document as VHDLModel_Document
 
 from pyGHDL.libghdl import (
     ENCODING,
@@ -70,7 +67,7 @@ from pyGHDL.libghdl.vhdl import nodes, sem_lib
 from pyGHDL.libghdl.vhdl.parse import Flag_Parse_Parenthesis
 from pyGHDL.dom import DOMException, Position
 from pyGHDL.dom._Utils import GetIirKindOfNode, CheckForErrors, GetNameOfNode, GetDocumentationOfNode
-from pyGHDL.dom.Names import SimpleName
+from pyGHDL.dom.Symbol import LibraryReferenceSymbol
 from pyGHDL.dom.DesignUnit import (
     Entity,
     Architecture,
@@ -83,7 +80,6 @@ from pyGHDL.dom.DesignUnit import (
     UseClause,
     ContextReference,
 )
-from pyGHDL.dom.Symbol import LibraryReferenceSymbol
 from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode
 
 
diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index 953fae02a..f1028c305 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -34,16 +34,14 @@ from typing import Union, List, Iterable
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    Constant as VHDLModel_Constant,
-    DeferredConstant as VHDLModel_DeferredConstant,
-    Variable as VHDLModel_Variable,
-    SharedVariable as VHDLModel_SharedVariable,
-    Signal as VHDLModel_Signal,
-    File as VHDLModel_File,
-    ExpressionUnion,
-    SubtypeOrSymbol,
-)
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Object import Constant as VHDLModel_Constant
+from pyVHDLModel.Object import DeferredConstant as VHDLModel_DeferredConstant
+from pyVHDLModel.Object import Variable as VHDLModel_Variable
+from pyVHDLModel.Object import SharedVariable as VHDLModel_SharedVariable
+from pyVHDLModel.Object import Signal as VHDLModel_Signal
+from pyVHDLModel.Object import File as VHDLModel_File
 
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
@@ -57,7 +55,7 @@ class Constant(VHDLModel_Constant, DOMMixin):
         self,
         node: Iir,
         identifiers: List[str],
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion,
         documentation: str = None,
     ):
@@ -90,7 +88,7 @@ class Constant(VHDLModel_Constant, DOMMixin):
 
 @export
 class DeferredConstant(VHDLModel_DeferredConstant, DOMMixin):
-    def __init__(self, node: Iir, identifiers: List[str], subtype: SubtypeOrSymbol, documentation: str = None):
+    def __init__(self, node: Iir, identifiers: List[str], subtype: Symbol, documentation: str = None):
         super().__init__(identifiers, subtype, documentation)
         DOMMixin.__init__(self, node)
 
@@ -114,7 +112,7 @@ class Variable(VHDLModel_Variable, DOMMixin):
         self,
         node: Iir,
         identifiers: List[str],
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion,
         documentation: str = None,
     ):
@@ -144,7 +142,7 @@ class Variable(VHDLModel_Variable, DOMMixin):
 
 @export
 class SharedVariable(VHDLModel_SharedVariable, DOMMixin):
-    def __init__(self, node: Iir, identifiers: List[str], subtype: SubtypeOrSymbol, documentation: str = None):
+    def __init__(self, node: Iir, identifiers: List[str], subtype: Symbol, documentation: str = None):
         super().__init__(identifiers, subtype, documentation)
         DOMMixin.__init__(self, node)
 
@@ -168,7 +166,7 @@ class Signal(VHDLModel_Signal, DOMMixin):
         self,
         node: Iir,
         identifiers: List[str],
-        subtype: SubtypeOrSymbol,
+        subtype: Symbol,
         defaultExpression: ExpressionUnion,
         documentation: str = None,
     ):
@@ -196,7 +194,7 @@ class Signal(VHDLModel_Signal, DOMMixin):
 
 @export
 class File(VHDLModel_File, DOMMixin):
-    def __init__(self, node: Iir, identifiers: List[str], subtype: SubtypeOrSymbol, documentation: str = None):
+    def __init__(self, node: Iir, identifiers: List[str], subtype: Symbol, documentation: str = None):
         super().__init__(identifiers, subtype, documentation)
         DOMMixin.__init__(self, node)
 
diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py
index f935f7849..cfd5e569c 100644
--- a/pyGHDL/dom/PSL.py
+++ b/pyGHDL/dom/PSL.py
@@ -41,12 +41,10 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 """
 from pyTooling.Decorators import export
 
-from pyVHDLModel.PSLModel import (
-    VerificationUnit as VHDLModel_VerificationUnit,
-    VerificationProperty as VHDLModel_VerificationProperty,
-    VerificationMode as VHDLModel_VerificationMode,
-    DefaultClock as VHDLModel_DefaultClock,
-)
+from pyVHDLModel.PSLModel import VerificationUnit as VHDLModel_VerificationUnit
+from pyVHDLModel.PSLModel import VerificationProperty as VHDLModel_VerificationProperty
+from pyVHDLModel.PSLModel import VerificationMode as VHDLModel_VerificationMode
+from pyVHDLModel.PSLModel import DefaultClock as VHDLModel_DefaultClock
 
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py
index 2674a43f4..d43031c06 100644
--- a/pyGHDL/dom/Range.py
+++ b/pyGHDL/dom/Range.py
@@ -32,7 +32,7 @@
 # ============================================================================
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import Range as VHDLModel_Range
+from pyVHDLModel.Base import Range as VHDLModel_Range
 
 
 @export
diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py
index 296f57f52..b698f1771 100644
--- a/pyGHDL/dom/Sequential.py
+++ b/pyGHDL/dom/Sequential.py
@@ -34,40 +34,32 @@ from typing import Iterable
 
 from pyTooling.Decorators import export
 
-from pyGHDL.dom.Concurrent import (
-    WaveformElement,
-    ParameterAssociationItem,
-)  # TODO: move out from concurrent?
-from pyGHDL.dom.Range import Range
-from pyVHDLModel.SyntaxModel import (
-    IfBranch as VHDLModel_IfBranch,
-    ElsifBranch as VHDLModel_ElsifBranch,
-    ElseBranch as VHDLModel_ElseBranch,
-    IfStatement as VHDLModel_IfStatement,
-    IndexedChoice as VHDLModel_IndexedChoice,
-    RangedChoice as VHDLModel_RangedChoice,
-    OthersCase as VHDLModel_OthersCase,
-    Case as VHDLModel_Case,
-    CaseStatement as VHDLModel_CaseStatement,
-    ForLoopStatement as VHDLModel_ForLoopStatement,
-    SequentialSimpleSignalAssignment as VHDLModel_SequentialSimpleSignalAssignment,
-    SequentialProcedureCall as VHDLModel_SequentialProcedureCall,
-    SequentialAssertStatement as VHDLModel_SequentialAssertStatement,
-    SequentialReportStatement as VHDLModel_SequentialReportStatement,
-    NullStatement as VHDLModel_NullStatement,
-    WaitStatement as VHDLModel_WaitStatement,
-    Name,
-    SequentialStatement,
-    ExpressionUnion,
-    SequentialChoice,
-    SequentialCase,
-)
-
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Sequential import SequentialStatement, SequentialChoice, SequentialCase
+from pyVHDLModel.Sequential import IfBranch as VHDLModel_IfBranch
+from pyVHDLModel.Sequential import ElsifBranch as VHDLModel_ElsifBranch
+from pyVHDLModel.Sequential import ElseBranch as VHDLModel_ElseBranch
+from pyVHDLModel.Sequential import IndexedChoice as VHDLModel_IndexedChoice
+from pyVHDLModel.Sequential import RangedChoice as VHDLModel_RangedChoice
+from pyVHDLModel.Sequential import Case as VHDLModel_Case
+from pyVHDLModel.Sequential import OthersCase as VHDLModel_OthersCase
+from pyVHDLModel.Sequential import IfStatement as VHDLModel_IfStatement
+from pyVHDLModel.Sequential import CaseStatement as VHDLModel_CaseStatement
+from pyVHDLModel.Sequential import ForLoopStatement as VHDLModel_ForLoopStatement
+from pyVHDLModel.Sequential import NullStatement as VHDLModel_NullStatement
+from pyVHDLModel.Sequential import WaitStatement as VHDLModel_WaitStatement
+from pyVHDLModel.Sequential import SequentialProcedureCall as VHDLModel_SequentialProcedureCall
+from pyVHDLModel.Sequential import SequentialSimpleSignalAssignment as VHDLModel_SequentialSimpleSignalAssignment
+from pyVHDLModel.Sequential import SequentialReportStatement as VHDLModel_SequentialReportStatement
+from pyVHDLModel.Sequential import SequentialAssertStatement as VHDLModel_SequentialAssertStatement
 
 from pyGHDL.libghdl import Iir, utils
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin, Position, DOMException
 from pyGHDL.dom._Utils import GetNameOfNode
+from pyGHDL.dom.Range import Range
+from pyGHDL.dom.Concurrent import WaveformElement, ParameterAssociationItem  # TODO: move out from concurrent?
 
 
 @export
@@ -379,7 +371,7 @@ class SequentialSimpleSignalAssignment(VHDLModel_SequentialSimpleSignalAssignmen
     def __init__(
         self,
         assignmentNode: Iir,
-        target: Name,
+        target: Symbol,
         waveform: Iterable[WaveformElement],
         label: str = None,
     ):
@@ -405,7 +397,7 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin):
     def __init__(
         self,
         callNode: Iir,
-        procedureName: Name,
+        procedureName: Symbol,
         parameterMappings: Iterable[ParameterAssociationItem],
         label: str = None,
     ):
@@ -490,7 +482,7 @@ class WaitStatement(VHDLModel_WaitStatement, DOMMixin):
     def __init__(
         self,
         waitNode: Iir,
-        sensitivityList: Iterable[Name] = None,
+        sensitivityList: Iterable[Symbol] = None,
         condition: ExpressionUnion = None,
         timeout: ExpressionUnion = None,
         label: str = None,
diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py
index 46ce92707..17661b8b2 100644
--- a/pyGHDL/dom/Subprogram.py
+++ b/pyGHDL/dom/Subprogram.py
@@ -34,13 +34,10 @@ from typing import List
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    Function as VHDLModel_Function,
-    Procedure as VHDLModel_Procedure,
-    SubtypeOrSymbol,
-    GenericInterfaceItem,
-    ParameterInterfaceItem,
-)
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Interface import GenericInterfaceItem, ParameterInterfaceItem
+from pyVHDLModel.Subprogram import Procedure as VHDLModel_Procedure, Function as VHDLModel_Function
+
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin
@@ -54,7 +51,7 @@ class Function(VHDLModel_Function, DOMMixin):
         self,
         node: Iir,
         functionName: str,
-        returnType: SubtypeOrSymbol,
+        returnType: Symbol,
         genericItems: List[GenericInterfaceItem] = None,
         parameterItems: List[ParameterInterfaceItem] = None,
         documentation: str = None,
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index 76f794650..e62ec4137 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -30,30 +30,29 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
-from typing import List, Iterator
+from typing import List, Iterator, Iterable
 
 from pyTooling.Decorators import export, InheritDocString
 
-from pyVHDLModel.SyntaxModel import (
-    SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol,
-    ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol,
-    ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol,
-    SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol,
-    IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol,
-    ConstraintUnion,
-    Name,
-    LibraryReferenceSymbol as VHDLModel_LibraryReferenceSymbol,
-    PackageReferenceSymbol as VHDLModel_PackageReferenceSymbol,
-    PackageMembersReferenceSymbol as VHDLModel_PackageMembersReferenceSymbol,
-    AllPackageMembersReferenceSymbol as VHDLModel_AllPackageMembersReferenceSymbol,
-    ContextReferenceSymbol as VHDLModel_ContextReferenceSymbol,
-    EntityInstantiationSymbol as VHDLModel_EntityInstantiationSymbol,
-    ComponentInstantiationSymbol as VHDLModel_ComponentInstantiationSymbol,
-    ConfigurationInstantiationSymbol as VHDLModel_ConfigurationInstantiationSymbol,
-    EntitySymbol as VHDLModel_EntitySymbol,
-    ArchitectureSymbol as VHDLModel_ArchitectureSymbol,
-    PackageSymbol as VHDLModel_PackageSymbol,
-)
+from pyVHDLModel import Name
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import LibraryReferenceSymbol as VHDLModel_LibraryReferenceSymbol
+from pyVHDLModel.Symbol import PackageReferenceSymbol as VHDLModel_PackageReferenceSymbol
+from pyVHDLModel.Symbol import PackageMembersReferenceSymbol as VHDLModel_PackageMembersReferenceSymbol
+from pyVHDLModel.Symbol import AllPackageMembersReferenceSymbol as VHDLModel_AllPackageMembersReferenceSymbol
+from pyVHDLModel.Symbol import ContextReferenceSymbol as VHDLModel_ContextReferenceSymbol
+from pyVHDLModel.Symbol import EntitySymbol as VHDLModel_EntitySymbol
+from pyVHDLModel.Symbol import ArchitectureSymbol as VHDLModel_ArchitectureSymbol
+from pyVHDLModel.Symbol import PackageSymbol as VHDLModel_PackageSymbol
+from pyVHDLModel.Symbol import EntityInstantiationSymbol as VHDLModel_EntityInstantiationSymbol
+from pyVHDLModel.Symbol import ComponentInstantiationSymbol as VHDLModel_ComponentInstantiationSymbol
+from pyVHDLModel.Symbol import ConfigurationInstantiationSymbol as VHDLModel_ConfigurationInstantiationSymbol
+from pyVHDLModel.Symbol import SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol
+from pyVHDLModel.Symbol import ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol
+from pyVHDLModel.Symbol import ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol
+from pyVHDLModel.Symbol import SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol
+from pyVHDLModel.Symbol import IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol
+
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom.Range import Range
@@ -153,18 +152,18 @@ class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin):
 
 @export
 class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin):
-    def __init__(self, node: Iir, subtypeName: Name):
+    def __init__(self, node: Iir, subtypeName: str):
         if isinstance(subtypeName, (List, Iterator)):
             subtypeName = ".".join(subtypeName)
 
-        super().__init__(subtypeName=subtypeName)
+        super().__init__(subtypeName)
         DOMMixin.__init__(self, node)
 
 
 @export
 class ConstrainedScalarSubtypeSymbol(VHDLModel_ConstrainedScalarSubtypeSymbol, DOMMixin):
     def __init__(self, node: Iir, subtypeName: Name, rng: Range = None):
-        super().__init__(subtypeName, rng)
+        super().__init__(subtypeName)  # , rng)  # XXX: hacked
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -174,8 +173,8 @@ class ConstrainedScalarSubtypeSymbol(VHDLModel_ConstrainedScalarSubtypeSymbol, D
 
 @export
 class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin):
-    def __init__(self, node: Iir, subtypeName: Name, constraints: List[ConstraintUnion] = None):
-        super().__init__(subtypeName, constraints)
+    def __init__(self, node: Iir, subtypeName: Name, constraints: List = None):
+        super().__init__(subtypeName)  # , constraints)  # XXX: hacked
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -185,18 +184,23 @@ class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSym
 
 @export
 class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin):
+    def __init__(self, node: Iir, identifier: str):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
     @classmethod
     def parse(cls, node: Iir):
         from pyGHDL.dom._Translate import GetNameFromNode
 
         name = GetNameFromNode(node)
-        return cls(name)
+
+        return cls(node, str(name))  # XXX: hacked
 
 
 @export
 class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin):
-    def __init__(self, node: Iir, name: Name):
-        super().__init__(name)
+    def __init__(self, node: Iir, prefix: Name, indices: Iterable[ExpressionUnion]):
+        super().__init__(prefix, indices)
         DOMMixin.__init__(self, node)
 
     @classmethod
@@ -205,4 +209,4 @@ class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSym
 
         name = GetNameFromNode(node)
 
-        return cls(node, name)
+        return cls(node, name, [])
diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py
index 2b71ccc3c..e7d9701fd 100644
--- a/pyGHDL/dom/Type.py
+++ b/pyGHDL/dom/Type.py
@@ -34,22 +34,21 @@ from typing import List, Union, Iterator, Tuple, Iterable
 
 from pyTooling.Decorators import export
 
-from pyVHDLModel.SyntaxModel import (
-    AnonymousType as VHDLModel_AnonymousType,
-    PhysicalType as VHDLModel_PhysicalType,
-    IntegerType as VHDLModel_IntegerType,
-    EnumeratedType as VHDLModel_EnumeratedType,
-    ArrayType as VHDLModel_ArrayType,
-    RecordTypeElement as VHDLModel_RecordTypeElement,
-    RecordType as VHDLModel_RecordType,
-    AccessType as VHDLModel_AccessType,
-    FileType as VHDLModel_FileType,
-    ProtectedType as VHDLModel_ProtectedType,
-    ProtectedTypeBody as VHDLModel_ProtectedTypeBody,
-    Subtype as VHDLModel_Subtype,
-    SubtypeOrSymbol,
-    Name,
-)
+from pyVHDLModel.Name import Name
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Type import Subtype as VHDLModel_Subtype
+from pyVHDLModel.Type import AnonymousType as VHDLModel_AnonymousType
+from pyVHDLModel.Type import EnumeratedType as VHDLModel_EnumeratedType
+from pyVHDLModel.Type import IntegerType as VHDLModel_IntegerType
+from pyVHDLModel.Type import PhysicalType as VHDLModel_PhysicalType
+from pyVHDLModel.Type import ArrayType as VHDLModel_ArrayType
+from pyVHDLModel.Type import RecordTypeElement as VHDLModel_RecordTypeElement
+from pyVHDLModel.Type import RecordType as VHDLModel_RecordType
+from pyVHDLModel.Type import ProtectedType as VHDLModel_ProtectedType
+from pyVHDLModel.Type import ProtectedTypeBody as VHDLModel_ProtectedTypeBody
+from pyVHDLModel.Type import AccessType as VHDLModel_AccessType
+from pyVHDLModel.Type import FileType as VHDLModel_FileType
+
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes, flists
@@ -148,7 +147,7 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin):
 
 @export
 class ArrayType(VHDLModel_ArrayType, DOMMixin):
-    def __init__(self, node: Iir, identifier: str, indices: List, elementSubtype: SubtypeOrSymbol):
+    def __init__(self, node: Iir, identifier: str, indices: List, elementSubtype: Symbol):
         super().__init__(identifier, indices, elementSubtype)
         DOMMixin.__init__(self, node)
 
@@ -180,7 +179,7 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin):
 
 @export
 class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin):
-    def __init__(self, node: Iir, identifiers: List[str], subtype: SubtypeOrSymbol):
+    def __init__(self, node: Iir, identifiers: List[str], subtype: Symbol):
         super().__init__(identifiers, subtype)
         DOMMixin.__init__(self, node)
 
@@ -288,7 +287,7 @@ class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin):
 
 @export
 class AccessType(VHDLModel_AccessType, DOMMixin):
-    def __init__(self, node: Iir, identifier: str, designatedSubtype: SubtypeOrSymbol):
+    def __init__(self, node: Iir, identifier: str, designatedSubtype: Symbol):
         super().__init__(identifier, designatedSubtype)
         DOMMixin.__init__(self, node)
 
@@ -304,7 +303,7 @@ class AccessType(VHDLModel_AccessType, DOMMixin):
 
 @export
 class FileType(VHDLModel_FileType, DOMMixin):
-    def __init__(self, node: Iir, identifier: str, designatedSubtype: SubtypeOrSymbol):
+    def __init__(self, node: Iir, identifier: str, designatedSubtype: Symbol):
         super().__init__(identifier, designatedSubtype)
         DOMMixin.__init__(self, node)
 
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 6d3ced3ef..8bdf221f3 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -34,6 +34,18 @@ from typing import List, Generator, Type
 
 from pyTooling.Decorators import export
 
+from pyVHDLModel import Name
+from pyVHDLModel.Base import ModelEntity, Direction, ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Association import AssociationItem
+from pyVHDLModel.Interface import GenericInterfaceItem, PortInterfaceItem, ParameterInterfaceItem
+from pyVHDLModel.Type import BaseType
+from pyVHDLModel.Sequential import SequentialStatement
+from pyVHDLModel.Concurrent import ConcurrentStatement
+
+from pyGHDL.libghdl import utils, name_table
+from pyGHDL.libghdl._types import Iir
+from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom.Sequential import (
     IfStatement,
     ForLoopStatement,
@@ -45,30 +57,9 @@ from pyGHDL.dom.Sequential import (
     NullStatement,
     SequentialProcedureCall,
 )
-from pyVHDLModel.SyntaxModel import (
-    ConstraintUnion,
-    Direction,
-    ExpressionUnion,
-    SubtypeOrSymbol,
-    BaseType,
-    GenericInterfaceItem,
-    PortInterfaceItem,
-    ParameterInterfaceItem,
-    ModelEntity,
-    Name,
-    ConcurrentStatement,
-    SequentialStatement,
-    AssociationItem,
-)
 
-from pyGHDL.libghdl import utils, name_table
-from pyGHDL.libghdl._types import Iir
-from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import Position, DOMException
-from pyGHDL.dom._Utils import (
-    GetNameOfNode,
-    GetIirKindOfNode,
-)
+from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode
 from pyGHDL.dom.Names import (
     SimpleName,
     SelectedName,
@@ -223,7 +214,7 @@ def GetAssociations(node: Iir) -> List:
 @export
 def GetArrayConstraintsFromSubtypeIndication(
     subtypeIndication: Iir,
-) -> List[ConstraintUnion]:
+) -> List:
     constraints = []
     for constraint in utils.flist_iter(nodes.Get_Index_Constraint_List(subtypeIndication)):
         constraintKind = GetIirKindOfNode(constraint)
@@ -303,13 +294,13 @@ def GetAnonymousTypeFromNode(node: Iir) -> BaseType:
 
 
 @export
-def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubtypeOrSymbol:
+def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> Symbol:
     subtypeIndicationNode = nodes.Get_Subtype_Indication(node)
     return GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode, entity, name)
 
 
 @export
-def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: str, name: str) -> SubtypeOrSymbol:
+def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: str, name: str) -> Symbol:
     if subtypeIndicationNode is nodes.Null_Iir:
         raise ValueError("Parameter 'subtypeIndicationNode' is 'Null_Iir'.")
 
@@ -331,7 +322,7 @@ def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: s
 @export
 def GetSimpleTypeFromNode(subtypeIndicationNode: Iir) -> SimpleSubtypeSymbol:
     subtypeName = GetNameFromNode(subtypeIndicationNode)
-    return SimpleSubtypeSymbol(subtypeIndicationNode, subtypeName)
+    return SimpleSubtypeSymbol(subtypeIndicationNode, str(subtypeName))  # XXX: hacked
 
 
 @export
@@ -343,7 +334,7 @@ def GetScalarConstrainedSubtypeFromNode(
     simpleTypeMark = SimpleName(typeMark, typeMarkName)
     rangeConstraint = nodes.Get_Range_Constraint(subtypeIndicationNode)
     r = GetRangeFromNode(rangeConstraint)
-    return ConstrainedScalarSubtypeSymbol(subtypeIndicationNode, simpleTypeMark, r)
+    return ConstrainedScalarSubtypeSymbol(subtypeIndicationNode, str(simpleTypeMark), r)  # XXX: hacked
 
 
 @export
@@ -355,11 +346,11 @@ def GetCompositeConstrainedSubtypeFromNode(
     simpleTypeMark = SimpleName(typeMark, typeMarkName)
 
     constraints = GetArrayConstraintsFromSubtypeIndication(subtypeIndicationNode)
-    return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, simpleTypeMark, constraints)
+    return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, str(simpleTypeMark), constraints)  # XXX: hacked
 
 
 @export
-def GetSubtypeFromNode(subtypeNode: Iir) -> SubtypeOrSymbol:
+def GetSubtypeFromNode(subtypeNode: Iir) -> Symbol:
     subtypeName = GetNameOfNode(subtypeNode)
 
     return Subtype(subtypeNode, subtypeName)
diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py
index 09f336c03..7ab02ace9 100644
--- a/pyGHDL/dom/_Utils.py
+++ b/pyGHDL/dom/_Utils.py
@@ -34,6 +34,13 @@ from typing import Union
 
 from pyTooling.Decorators import export
 
+from pyVHDLModel.Base import Mode
+
+from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments
+from pyGHDL.libghdl._types import Iir
+from pyGHDL.libghdl.vhdl import nodes, utils
+from pyGHDL.libghdl.vhdl.nodes import Null_Iir
+from pyGHDL.dom import DOMException, Position
 from pyGHDL.dom.Symbol import (
     LibraryReferenceSymbol,
     PackageReferenceSymbol,
@@ -44,13 +51,7 @@ from pyGHDL.dom.Symbol import (
     ComponentInstantiationSymbol,
     ConfigurationInstantiationSymbol,
 )
-from pyVHDLModel.SyntaxModel import Mode
 
-from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments
-from pyGHDL.libghdl._types import Iir
-from pyGHDL.libghdl.vhdl import nodes, utils
-from pyGHDL.libghdl.vhdl.nodes import Null_Iir
-from pyGHDL.dom import DOMException, Position
 
 __MODE_TRANSLATION = {
     nodes.Iir_Mode.In_Mode: Mode.In,
diff --git a/pyGHDL/dom/formatting/GraphML.py b/pyGHDL/dom/formatting/GraphML.py
new file mode 100644
index 000000000..7f72d54b5
--- /dev/null
+++ b/pyGHDL/dom/formatting/GraphML.py
@@ -0,0 +1,340 @@
+from pathlib import Path
+from textwrap import dedent
+from typing import Dict, List
+
+from pyTooling.Graph import Graph, Vertex
+
+from pyVHDLModel import (
+    DependencyGraphVertexKind,
+    DependencyGraphEdgeKind,
+    Library as VHDLModel_Library,
+    Document as VHDLModel_Document,
+)
+
+
+class DependencyGraphFormatter:
+    _graph: Graph
+
+    NODE_COLORS = {
+        DependencyGraphVertexKind.Document: "#999999",
+        DependencyGraphVertexKind.Library: "#99ccff",
+        DependencyGraphVertexKind.Package: "#ff9900",
+        DependencyGraphVertexKind.PackageBody: "#ff9900",
+        DependencyGraphVertexKind.Context: "#cc99ff",
+        DependencyGraphVertexKind.Entity: "#ffff99",
+        DependencyGraphVertexKind.Architecture: "#ff99cc",
+        DependencyGraphVertexKind.Configuration: "#ff9900",
+    }
+    EDGE_COLORS = {
+        DependencyGraphEdgeKind.SourceFile: "#000000",
+        DependencyGraphEdgeKind.CompileOrder: "#ff0000",
+        DependencyGraphEdgeKind.LibraryClause: "#000000",
+        DependencyGraphEdgeKind.UseClause: "#000000",
+        DependencyGraphEdgeKind.ContextReference: "#000000",
+        DependencyGraphEdgeKind.EntityImplementation: "#99ccff",
+        DependencyGraphEdgeKind.PackageImplementation: "#99ccff",
+        DependencyGraphEdgeKind.EntityInstantiation: "#000000",
+        DependencyGraphEdgeKind.ComponentInstantiation: "#000000",
+        DependencyGraphEdgeKind.ConfigurationInstantiation: "#000000",
+    }
+
+    def __init__(self, graph: Graph):
+        self._graph = graph
+
+    def WriteGraphML(self, path: Path):
+        with path.open("w") as file:
+            file.write(
+                dedent(
+                    f"""\
+            <graphml xmlns="http://graphml.graphdrawing.org/xmlns"
+                     xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+                     xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
+              <key id="nd1" for="node" attr.name="id" attr.type="string"/>
+              <key id="nd2" for="node" attr.name="value" attr.type="string"/>
+              <key id="nd3" for="node" attr.name="kind" attr.type="string"/>
+              <key id="nd4" for="node" attr.name="color" attr.type="string"/>
+
+              <key id="ed3" for="edge" attr.name="kind" attr.type="string"/>
+              <key id="ed4" for="edge" attr.name="color" attr.type="string"/>
+              <graph id="DependencyGraph"
+                     edgedefault="directed"
+                     parse.nodes="{len(self._graph._verticesWithID)}"
+                     parse.edges="{len(self._graph._edgesWithoutID)}"
+                     parse.order="nodesfirst">
+            """
+                )
+            )
+            groups: Dict[str, List[Vertex]] = {}
+            for vertex in self._graph._verticesWithID.values():
+                if isinstance(vertex.Value, VHDLModel_Library):
+                    identifier = vertex.Value.NormalizedIdentifier
+                elif isinstance(vertex.Value, VHDLModel_Document):
+                    identifier = vertex.Value.DesignUnits[0].Library.NormalizedIdentifier
+                else:
+                    identifier = vertex.Value.Library.NormalizedIdentifier
+
+                if identifier in groups:
+                    groups[identifier].append(vertex)
+                else:
+                    groups[identifier] = [vertex]
+
+            for group, vertices in groups.items():
+                file.write(
+                    dedent(
+                        """\
+                    {prefix}<node id="grp_{id}">
+                    {prefix}  <data key="nd2">{value}</data>
+                    {prefix}  <graph id="{id}" edgedefault="directed">
+                """
+                    ).format(prefix="    ", id=group, value=group)
+                )
+
+                for vertex in vertices:
+                    if vertex["kind"] is DependencyGraphVertexKind.Architecture:
+                        value = f"{vertex.Value.Entity.Identifier}({vertex.Value.Identifier})"
+                    elif vertex["kind"] is DependencyGraphVertexKind.Document:
+                        value = f"{vertex.ID}"
+                    else:
+                        value = f"{vertex.Value.Identifier}"
+                    file.write(
+                        dedent(
+                            """\
+                        {prefix}<node id="{vertex.ID}">
+                        {prefix}  <data key="nd1">{vertex.ID}</data>
+                        {prefix}  <data key="nd2">{value}</data>
+                        {prefix}  <data key="nd3">{vertex[kind].name}</data>
+                        {prefix}  <data key="nd4">{color}</data>
+                        {prefix}</node>
+                    """
+                        ).format(prefix="        ", vertex=vertex, value=value, color=self.NODE_COLORS[vertex["kind"]])
+                    )
+
+                file.write(
+                    dedent(
+                        """\
+                    {prefix}  </graph>
+                    {prefix}</node>
+                """
+                    ).format(prefix="    ")
+                )
+
+            edgeCount = 1
+            for edge in self._graph._edgesWithoutID:
+                file.write(
+                    dedent(
+                        """\
+                    {prefix}<edge id="e{edgeCount}" source="{edge.Source.ID}" target="{edge.Destination.ID}">
+                    {prefix}  <data key="ed3">{edge[kind].name}</data>
+                    {prefix}  <data key="ed4">{color}</data>
+                    {prefix}</edge>
+                """
+                    ).format(prefix="    ", edgeCount=edgeCount, edge=edge, color=self.EDGE_COLORS[edge["kind"]])
+                )
+                edgeCount += 1
+
+            file.write(
+                dedent(
+                    """\
+              </graph>
+            </graphml>
+            """
+                )
+            )
+
+
+class HierarchyGraphFormatter:
+    _graph: Graph
+
+    NODE_COLORS = {
+        DependencyGraphVertexKind.Document: "#999999",
+        DependencyGraphVertexKind.Library: "#99ccff",
+        DependencyGraphVertexKind.Package: "#ff9900",
+        DependencyGraphVertexKind.PackageBody: "#ff9900",
+        DependencyGraphVertexKind.Context: "#cc99ff",
+        DependencyGraphVertexKind.Entity: "#ffff99",
+        DependencyGraphVertexKind.Architecture: "#ff99cc",
+        DependencyGraphVertexKind.Configuration: "#ff9900",
+    }
+    EDGE_COLORS = {
+        DependencyGraphEdgeKind.SourceFile: "#000000",
+        DependencyGraphEdgeKind.CompileOrder: "#ff0000",
+        DependencyGraphEdgeKind.LibraryClause: "#000000",
+        DependencyGraphEdgeKind.UseClause: "#000000",
+        DependencyGraphEdgeKind.ContextReference: "#000000",
+        DependencyGraphEdgeKind.EntityImplementation: "#99ccff",
+        DependencyGraphEdgeKind.PackageImplementation: "#99ccff",
+        DependencyGraphEdgeKind.EntityInstantiation: "#000000",
+        DependencyGraphEdgeKind.ComponentInstantiation: "#000000",
+        DependencyGraphEdgeKind.ConfigurationInstantiation: "#000000",
+    }
+
+    def __init__(self, graph: Graph):
+        self._graph = graph
+
+    def WriteGraphML(self, path: Path):
+        with path.open("w") as file:
+            file.write(
+                dedent(
+                    f"""\
+            <graphml xmlns="http://graphml.graphdrawing.org/xmlns"
+                     xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+                     xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
+              <key id="nd1" for="node" attr.name="id" attr.type="string"/>
+              <key id="nd2" for="node" attr.name="value" attr.type="string"/>
+              <key id="nd3" for="node" attr.name="kind" attr.type="string"/>
+              <key id="nd4" for="node" attr.name="color" attr.type="string"/>
+
+              <key id="ed3" for="edge" attr.name="kind" attr.type="string"/>
+              <key id="ed4" for="edge" attr.name="color" attr.type="string"/>
+              <graph id="HierarchyGraph"
+                     edgedefault="directed"
+                     parse.nodes="{len(self._graph._verticesWithID)}"
+                     parse.edges="{len(self._graph._edgesWithoutID)}"
+                     parse.order="nodesfirst">
+            """
+                )
+            )
+
+            for vertex in self._graph._verticesWithID.values():
+                if vertex["kind"] is DependencyGraphVertexKind.Entity:
+                    file.write(
+                        dedent(
+                            """\
+                        {prefix}<node id="{vertex.ID}">
+                        {prefix}  <data key="nd1">{vertex.ID}</data>
+                        {prefix}  <data key="nd2">{vertex.Value.Identifier}</data>
+                        {prefix}  <data key="nd3">{vertex[kind].name}</data>
+                        {prefix}  <data key="nd4">{color}</data>
+                        {prefix}</node>
+                    """
+                        ).format(prefix="    ", vertex=vertex, color=self.NODE_COLORS[vertex["kind"]])
+                    )
+                elif vertex["kind"] is DependencyGraphVertexKind.Architecture:
+                    file.write(
+                        dedent(
+                            """\
+                        {prefix}<node id="{vertex.ID}">
+                        {prefix}  <data key="nd1">{vertex.ID}</data>
+                        {prefix}  <data key="nd2">{vertex.Value.Identifier}</data>
+                        {prefix}  <data key="nd3">{vertex[kind].name}</data>
+                        {prefix}  <data key="nd4">{color}</data>
+                        {prefix}</node>
+                    """
+                        ).format(prefix="    ", vertex=vertex, color=self.NODE_COLORS[vertex["kind"]])
+                    )
+
+            edgeCount = 1
+            for edge in self._graph._edgesWithoutID:
+                file.write(
+                    dedent(
+                        """\
+                    {prefix}<edge id="e{edgeCount}" source="{edge.Source.ID}" target="{edge.Destination.ID}">
+                    {prefix}  <data key="ed3">{edge[kind].name}</data>
+                    {prefix}  <data key="ed4">{color}</data>
+                    {prefix}</edge>
+                """
+                    ).format(prefix="    ", edgeCount=edgeCount, edge=edge, color=self.EDGE_COLORS[edge["kind"]])
+                )
+                edgeCount += 1
+
+            file.write(
+                dedent(
+                    """\
+              </graph>
+            </graphml>
+            """
+                )
+            )
+
+
+class CompileOrderGraphFormatter:
+    _graph: Graph
+
+    NODE_COLORS = {
+        DependencyGraphVertexKind.Document: "#999999",
+        DependencyGraphVertexKind.Library: "#99ccff",
+        DependencyGraphVertexKind.Package: "#ff9900",
+        DependencyGraphVertexKind.PackageBody: "#ff9900",
+        DependencyGraphVertexKind.Context: "#cc99ff",
+        DependencyGraphVertexKind.Entity: "#ffff99",
+        DependencyGraphVertexKind.Architecture: "#ff99cc",
+        DependencyGraphVertexKind.Configuration: "#ff9900",
+    }
+    EDGE_COLORS = {
+        DependencyGraphEdgeKind.SourceFile: "#000000",
+        DependencyGraphEdgeKind.CompileOrder: "#ff0000",
+        DependencyGraphEdgeKind.LibraryClause: "#000000",
+        DependencyGraphEdgeKind.UseClause: "#000000",
+        DependencyGraphEdgeKind.ContextReference: "#000000",
+        DependencyGraphEdgeKind.EntityImplementation: "#99ccff",
+        DependencyGraphEdgeKind.PackageImplementation: "#99ccff",
+        DependencyGraphEdgeKind.EntityInstantiation: "#000000",
+        DependencyGraphEdgeKind.ComponentInstantiation: "#000000",
+        DependencyGraphEdgeKind.ConfigurationInstantiation: "#000000",
+    }
+
+    def __init__(self, graph: Graph):
+        self._graph = graph
+
+    def WriteGraphML(self, path: Path):
+        print(path.absolute())
+        with path.open("w") as file:
+            file.write(
+                dedent(
+                    f"""\
+            <graphml xmlns="http://graphml.graphdrawing.org/xmlns"
+                     xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+                     xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
+              <key id="nd1" for="node" attr.name="id" attr.type="string"/>
+              <key id="nd2" for="node" attr.name="value" attr.type="string"/>
+              <key id="nd3" for="node" attr.name="kind" attr.type="string"/>
+              <key id="nd4" for="node" attr.name="color" attr.type="string"/>
+
+              <key id="ed3" for="edge" attr.name="kind" attr.type="string"/>
+              <key id="ed4" for="edge" attr.name="color" attr.type="string"/>
+              <graph id="CompileOrderGraph"
+                     edgedefault="directed"
+                     parse.nodes="{len(self._graph._verticesWithID)}"
+                     parse.edges="{len(self._graph._edgesWithoutID)}"
+                     parse.order="nodesfirst">
+            """
+                )
+            )
+
+            for vertex in self._graph._verticesWithID.values():
+                if vertex["kind"] is DependencyGraphVertexKind.Document:
+                    file.write(
+                        dedent(
+                            """\
+                        {prefix}<node id="{vertex.ID}">
+                        {prefix}  <data key="nd1">{vertex.ID}</data>
+                        {prefix}  <data key="nd2">{vertex.Value.Path.name}</data>
+                        {prefix}  <data key="nd3">{vertex[kind].name}</data>
+                        {prefix}  <data key="nd4">{color}</data>
+                        {prefix}</node>
+                    """
+                        ).format(prefix="    ", vertex=vertex, color=self.NODE_COLORS[vertex["kind"]])
+                    )
+
+            edgeCount = 1
+            for edge in self._graph._edgesWithoutID:
+                file.write(
+                    dedent(
+                        """\
+                    {prefix}<edge id="e{edgeCount}" source="{edge.Source.ID}" target="{edge.Destination.ID}">
+                    {prefix}  <data key="ed3">{edge[kind].name}</data>
+                    {prefix}  <data key="ed4">{color}</data>
+                    {prefix}</edge>
+                """
+                    ).format(prefix="    ", edgeCount=edgeCount, edge=edge, color=self.EDGE_COLORS[edge["kind"]])
+                )
+                edgeCount += 1
+
+            file.write(
+                dedent(
+                    """\
+              </graph>
+            </graphml>
+            """
+                )
+            )
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index da26372c4..5be27492d 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -34,6 +34,15 @@ from typing import List, Union
 
 from pyTooling.Decorators import export
 
+from pyVHDLModel.Base import NamedEntityMixin
+from pyVHDLModel.Interface import GenericInterfaceItem, PortInterfaceItem
+from pyVHDLModel.Subprogram import Function
+from pyVHDLModel.Object import BaseConstant, WithDefaultExpressionMixin
+from pyVHDLModel.Type import BaseType, FullType
+from pyVHDLModel.Concurrent import ConcurrentStatement
+
+from pyGHDL import GHDLBaseException
+from pyGHDL.dom.NonStandard import Document, Design, Library
 from pyGHDL.dom.Concurrent import (
     ConcurrentBlockStatement,
     ProcessStatement,
@@ -45,20 +54,6 @@ from pyGHDL.dom.Concurrent import (
     EntityInstantiation,
     ConcurrentProcedureCall,
 )
-from pyVHDLModel.SyntaxModel import (
-    GenericInterfaceItem,
-    NamedEntityMixin,
-    PortInterfaceItem,
-    WithDefaultExpressionMixin,
-    Function,
-    BaseType,
-    FullType,
-    BaseConstant,
-    ConcurrentStatement,
-)
-
-from pyGHDL import GHDLBaseException
-from pyGHDL.dom.NonStandard import Document, Design, Library
 from pyGHDL.dom.DesignUnit import (
     Entity,
     Architecture,
@@ -70,10 +65,7 @@ from pyGHDL.dom.DesignUnit import (
     UseClause,
     PackageInstantiation,
 )
-from pyGHDL.dom.Symbol import (
-    SimpleSubtypeSymbol,
-    ConstrainedCompositeSubtypeSymbol,
-)
+from pyGHDL.dom.Symbol import SimpleSubtypeSymbol, ConstrainedCompositeSubtypeSymbol
 from pyGHDL.dom.Type import (
     IntegerType,
     Subtype,
diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt
index 90c229354..ec127c98c 100644
--- a/pyGHDL/dom/requirements.txt
+++ b/pyGHDL/dom/requirements.txt
@@ -1,4 +1,4 @@
 -r ../libghdl/requirements.txt
 
-pyVHDLModel==0.20.2
+pyVHDLModel==0.22.1
 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel
diff --git a/pyGHDL/libghdl/requirements.txt b/pyGHDL/libghdl/requirements.txt
index 5f5b740d6..9b79bd34d 100644
--- a/pyGHDL/libghdl/requirements.txt
+++ b/pyGHDL/libghdl/requirements.txt
@@ -1 +1 @@
-pyTooling>=2.1.0
+pyTooling>=2.11.0
diff --git a/pyproject.toml b/pyproject.toml
index 3d59efe58..699b7bfab 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,8 +1,8 @@
 [build-system]
 requires = [
-    "pyTooling >= 2.1.0",
+    "pyTooling >= 2.11.0",
     "setuptools >= 62.3.3",
-    "wheel >= 0.37.1"
+    "wheel >= 0.38.1"
 ]
 build-backend = "setuptools.build_meta"
 
diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py
index 4b2e47507..fe9bf22eb 100644
--- a/testsuite/pyunit/dom/Expressions.py
+++ b/testsuite/pyunit/dom/Expressions.py
@@ -97,7 +97,7 @@ class Expressions(TestCase):
         # Start checks
         self.assertIsInstance(default, InverseExpression)
         self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
-        self.assertEqual("true", str(default.Operand.SymbolName))
+        self.assertEqual("true", str(default.Operand))  # .SymbolName))  # XXX: hacked
 
     # def test_AbsExpression(self):
     #     filename: Path = self._root / "{className}_{funcName}.vhdl".format(
diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
index 9f53a6cc6..8d0b72fb0 100644
--- a/testsuite/pyunit/dom/Literals.py
+++ b/testsuite/pyunit/dom/Literals.py
@@ -35,13 +35,12 @@ from textwrap import dedent
 from typing import TypeVar, Dict
 from unittest import TestCase
 
-from pyVHDLModel.SyntaxModel import ExpressionUnion
-
-from pyGHDL.dom.DesignUnit import Package
+from pyVHDLModel.Base import ExpressionUnion
 
 from pyGHDL.dom.NonStandard import Design, Document
 from pyGHDL.dom.Object import Constant
 from pyGHDL.dom.Literal import IntegerLiteral
+from pyGHDL.dom.DesignUnit import Package
 
 
 if __name__ == "__main__":
diff --git a/testsuite/pyunit/dom/StopWatch.py b/testsuite/pyunit/dom/StopWatch.py
index 6301eb1df..deab50a9f 100644
--- a/testsuite/pyunit/dom/StopWatch.py
+++ b/testsuite/pyunit/dom/StopWatch.py
@@ -30,11 +30,20 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
+from time import perf_counter_ns as time_perf_counter
 from pathlib import Path
+from textwrap import dedent
+from typing import Dict, List
 from unittest import TestCase
 
+from pyTooling.Graph import Vertex
+
+import pyVHDLModel
+import pyVHDLModel.DesignUnit
 from pyGHDL.dom.NonStandard import Design, Document
+from pyGHDL.dom.formatting.GraphML import DependencyGraphFormatter, HierarchyGraphFormatter, CompileOrderGraphFormatter
 from pyGHDL.dom.formatting.prettyprint import PrettyPrint
+from pyVHDLModel import DependencyGraphVertexKind, DependencyGraphEdgeKind, Library
 
 if __name__ == "__main__":
     print("ERROR: you called a testcase declaration file as an executable module.")
@@ -106,19 +115,65 @@ class Display(Designs):
 
 class CompileOrder(Designs):
     def test_Encoder(self):
+        print()
         design = Design()
-        design.LoadStdLibrary()
-        design.LoadIEEELibrary()
-        for lib, file in self._encoderFiles:
+        design.LoadDefaultLibraries()
+        t1 = time_perf_counter()
+        for lib, file in self._stopwatchFiles:
             library = design.GetLibrary(lib)
             document = Document(self._sourceDirectory / file)
             design.AddDocument(document, library)
+            print(dedent("""\
+                file: {}
+                  libghdl processing time: {:5.3f} us
+                  DOM translation time:    {:5.3f} us
+                """
+                ).format(
+                    document.Path,
+                    document.LibGHDLProcessingTime * 10**6,
+                    document.DOMTranslationTime * 10**6,
+                )
+            )
+        pyGHDLTime = time_perf_counter() - t1
 
         design.Analyze()
 
-        PP = PrettyPrint()
-        buffer = []
-        buffer.append("Design:")
-        for line in PP.formatDesign(design, 1):
-            buffer.append(line)
-        print("\n".join(buffer))
+        toplevel = [root.Value.Identifier for root in design.HierarchyGraph.IterateRoots()]
+
+        print(dedent("""
+            pyGHDL:
+              sum:                       {:5.3f} us
+            Analysis:
+              default library load time: {:5.3f} us
+              dependency analysis time:  {:5.3f} us
+            Toplevel:                    {toplevel}
+            Compile order:\
+            """
+            ).format(
+                pyGHDLTime * 10**6,
+                design._loadDefaultLibraryTime * 10**6,
+                design._analyzeTime * 10**6,
+                toplevel=", ".join(toplevel)
+            )
+        )
+        for i, vertex in enumerate(design.IterateDocumentsInCompileOrder()):
+            print(f"  {i:<2}: {vertex.Value.Path.relative_to(Path.cwd())}")
+
+        graphML = Path("dependencies.graphml")
+        dependencyFormatter = DependencyGraphFormatter(design.DependencyGraph)
+        dependencyFormatter.WriteGraphML(graphML)
+
+        graphML = Path("hierarchy.graphml")
+        hierarchyFormatter = HierarchyGraphFormatter(design.HierarchyGraph)
+        hierarchyFormatter.WriteGraphML(graphML)
+
+        graphML = Path("compileorder.graphml")
+        compileOrderFormatter = CompileOrderGraphFormatter(design.CompileOrderGraph)
+        compileOrderFormatter.WriteGraphML(graphML)
+
+        # PP = PrettyPrint()
+        # buffer = []
+        # buffer.append("Design:")
+        # for line in PP.formatDesign(design, 1):
+        #     buffer.append(line)
+        # print("\n".join(buffer))
diff --git a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl
index ef1474164..2c4a0130f 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl
@@ -7,7 +7,7 @@ library IEEE;
 use     IEEE.std_logic_1164.all;
 use     IEEE.numeric_std.all;
 
-use     work.Utilities_pkg.all;
+context work.Utilities_ctx;
 
 
 entity Debouncer is
diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
index f67f99c72..3755e4575 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
@@ -30,4 +30,21 @@ package StopWatch_pkg is
 			Seg7Code  : out std_logic_vector(7 downto 0)
 		);
 	end component;
+
+	component seg7_Display is
+		generic (
+			CLOCK_PERIOD  : time := 10 ns;
+			REFRESH_RATE  : time := 200 us;
+			DIGITS        : positive
+		);
+		port (
+			Clock         : in  std_logic;
+
+			DigitValues   : in  T_BCD_Vector(DIGITS - 1 downto 0);
+			DotValues     : in  std_logic_vector(DIGITS - 1 downto 0) := (others => '0');
+
+			Seg7_Segments : out std_logic_vector(7 downto 0);
+			Seg7_Selects  : out std_logic_vector(DIGITS - 1 downto 0)
+		);
+	end component;
 end package;
diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl
index 3d73fa0fa..87a147833 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl
@@ -32,7 +32,7 @@ entity Stopwatch is
 end entity;
 
 
-architecture trl of Stopwatch is
+architecture rtl of Stopwatch is
 	type T_STATE is (ST_RESET, ST_IDLE, ST_COUNTING, ST_PAUSE);
 
 	signal State      : T_STATE := ST_IDLE;
@@ -92,7 +92,7 @@ begin
 		end case;
 	end process;
 
-	TimeBaseCnt: entity work.Counter
+	TimeBaseCnt: entity lib_Utilities.Counter
 		generic map (
 			MODULO     => TIMEBASE / (CLOCK_PERIOD * ite(IS_SIMULATION, 100, 1)),
 			BITS       => 0
@@ -109,7 +109,7 @@ begin
 	Overflows(0) <= Tick;
 
 	genDigits: for i in CONFIG'range generate
-		cnt: entity work.Counter
+		cnt: entity lib_Utilities.Counter
 			generic map (
 				MODULO     => CONFIG(i).Modulo,
 				BITS       => Digits(i)'length
diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl
index da21075cf..6ed4ecaba 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl
@@ -79,7 +79,7 @@ begin
 	Dot   <= DotValues(to_index(Digit_Select, DotValues'high));
 
 	-- 7-segment encoder
-	enc: configuration seg7_Encoder
+	enc: component seg7_Encoder
 		port map (
 			BCDValue  => Digit,
 			Dot       => Dot,
diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl
index 08046e2cc..d23d75b2e 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl
@@ -100,7 +100,7 @@ begin
 		);
 
 	-- 7-segment display
-	display: configuration seg7_Display_cfg
+	display: /* configuration */ seg7_Display--_cfg
 		generic map (
 			CLOCK_PERIOD  => CLOCK_PERIOD,
 			DIGITS        => Digits'length