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-rw-r--r--testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl6
1 files changed, 3 insertions, 3 deletions
diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl
index 3d73fa0fa..87a147833 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl
@@ -32,7 +32,7 @@ entity Stopwatch is
end entity;
-architecture trl of Stopwatch is
+architecture rtl of Stopwatch is
type T_STATE is (ST_RESET, ST_IDLE, ST_COUNTING, ST_PAUSE);
signal State : T_STATE := ST_IDLE;
@@ -92,7 +92,7 @@ begin
end case;
end process;
- TimeBaseCnt: entity work.Counter
+ TimeBaseCnt: entity lib_Utilities.Counter
generic map (
MODULO => TIMEBASE / (CLOCK_PERIOD * ite(IS_SIMULATION, 100, 1)),
BITS => 0
@@ -109,7 +109,7 @@ begin
Overflows(0) <= Tick;
genDigits: for i in CONFIG'range generate
- cnt: entity work.Counter
+ cnt: entity lib_Utilities.Counter
generic map (
MODULO => CONFIG(i).Modulo,
BITS => Digits(i)'length