first cut at spartan 6 fpga

15 files changed, 707 insertions, 763 deletions

diff --git a/ipad-5-or-air-1/README b/ipad-5-or-air-1/README
new file mode 100644
index 0000000..5af2cf7
--- /dev/null
+++ b/ipad-5-or-air-1/README
@@ -0,0 +1,16 @@
+Ipad Air 1st Gen model numbers
+
+A1474
+A1475
+A1476
+
+Ipad 5
+
+A1822
+A1823
+
+
+panel is  LP097QX2
+
+
+https://www.aliexpress.com/item/1005006418171265.html
diff --git a/smh-ac415-fpga/lcd_driver/Makefile b/smh-ac415-fpga/lcd_driver/Makefile
index 55c2402..530157e 100644
--- a/smh-ac415-fpga/lcd_driver/Makefile
+++ b/smh-ac415-fpga/lcd_driver/Makefile
@@ -1,5 +1,5 @@
 PROJECT = lcd_driver
-SOURCE_FILES = lcd_driver.vhdl 
+SOURCE_FILES = a_input.vhdl a_siggen.vhdl clk1.vhdl clk2.vhdl ddio_out.vhdl debounce.vhdl edge_det.vhdl hdmi_driver.vhdl lcd_driver.vhdl synchronizer.vhdl video_ram.vhdl
 ASSIGNMENT_FILES = lcd_driver.qpf lcd_driver.qsf 
 
 BUILD=output_files
diff --git a/smh-ac415-fpga/lcd_driver/a_clk_gen.vhdl b/smh-ac415-fpga/lcd_driver/a_clk_gen.vhdl
deleted file mode 100644
index 4918a95..0000000
--- a/smh-ac415-fpga/lcd_driver/a_clk_gen.vhdl
+++ /dev/null
@@ -1,366 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: a_clk_gen.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FIALE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web EditionA
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY a_clk_gen IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-END a_clk_gen;
-
-
-ARCHITECTURE SYN OF a_clk_gen IS
-
-	SIGNAL sub_wire0	: STD_LOGIC ;
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		self_reset_on_loss_lock		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC 
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire5_bv(0 DOWNTO 0) <= "0";
-	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
-	locked    <= sub_wire0;
-	sub_wire2    <= sub_wire1(0);
-	c0    <= sub_wire2;
-	sub_wire3    <= inclk0;
-	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 5,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 20000,
-		intended_device_family => "Cyclone IV E",
-		lpm_hint => "CBX_MODULE_PREFIX=a_clk_gen",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_USED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
-		port_clk2 => "PORT_UNUSED",
-		port_clk3 => "PORT_UNUSED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		self_reset_on_loss_lock => "ON",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire4,
-		locked => sub_wire0,
-		clk => sub_wire1
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "a_clk_gen.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
-
diff --git a/smh-ac415-fpga/lcd_driver/a_input.vhdl b/smh-ac415-fpga/lcd_driver/a_input.vhdl
index 15f1990..434d820 100644
--- a/smh-ac415-fpga/lcd_driver/a_input.vhdl
+++ b/smh-ac415-fpga/lcd_driver/a_input.vhdl
@@ -15,7 +15,7 @@ ENTITY a_input IS
 
 	PORT
 	(
-	  clk_50m : in std_logic;
+	  p_clk : in std_logic;
 	  sys_rst_n : in std_logic;
 	  video_in:in std_logic;
 	  bright_in:in std_logic;
@@ -32,14 +32,15 @@ END a_input;
 
 ARCHITECTURE beh OF a_input IS
 
-   signal p_clk : std_logic;
    signal p_clk_div : natural;
+   signal row_addr : std_logic_vector(17 downto 0)	;
    signal addr : std_logic_vector(17 downto 0)	;
    signal wren: std_logic;
 
 
  signal s_hsync: std_logic;
  signal d_hsync: std_logic;
+ signal pe_hsync: std_logic;
  signal ne_hsync: std_logic;
 
 
@@ -55,13 +56,6 @@ ARCHITECTURE beh OF a_input IS
 		
 begin
 
-
-	a_clk0: work.a_clk_gen
-	port map (
-		areset		=> not sys_rst_n,
-		inclk0 		=> clk_50m,
-		c0 => p_clk
-		);
 	
 
     video_sync: entity work.synchronizer
@@ -113,6 +107,7 @@ begin
         port map(
             clk => p_clk,
             sig => d_hsync,
+            pe  => pe_hsync,
             ne  => ne_hsync);
 
 
@@ -131,21 +126,25 @@ begin
 
 	process (sys_rst_n,p_clk,d_hsync,d_vsync)  begin
 	if sys_rst_n = '0' then
+		row_addr<=(others =>'0');
 		addr<=(others =>'0');
 		p_clk_div<=p_clk_multiple;
 		active_counter <=0;
 		fp_counter <=0;
 	elsif rising_edge(p_clk) then
 		if d_vsync='1' then
+			row_addr<=(others => '0');
 			addr<=(others => '0');
 			fp_counter <= front_porch;
 			active_counter <=hres;
 			p_clk_div <=p_clk_multiple;
+            	elsif pe_gsync ='1' then
+			row_addr <= std_logic_vector(unsigned(row_addr)+1);
 		elsif ne_hsync='1' then
 			fp_counter <= front_porch;
 			active_counter <=hres;
 			p_clk_div <=p_clk_multiple;
-			addr <= std_logic_vector(unsigned(addr)+1);
+			addr<=row_addr;
 		elsif fp_counter /= 0 then
 			fp_counter <= fp_counter -1;
 		elsif active_counter /= 0 then	
@@ -156,6 +155,8 @@ begin
 			else 
 				p_clk_div <= p_clk_div - 1;
 			end if;
+		else 
+			p_clk_div <=p_clk_multiple;
 		end if;
 	end if;
 	end process;
diff --git a/smh-ac415-fpga/lcd_driver/h_clk_gen.vhdl b/smh-ac415-fpga/lcd_driver/h_clk_gen.vhdl
deleted file mode 100644
index 05c08f4..0000000
--- a/smh-ac415-fpga/lcd_driver/h_clk_gen.vhdl
+++ /dev/null
@@ -1,366 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: h_clk_gen.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY h_clk_gen IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-END h_clk_gen;
-
-
-ARCHITECTURE SYN OF h_clk_gen IS
-
-	SIGNAL sub_wire0	: STD_LOGIC ;
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		self_reset_on_loss_lock		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC 
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire5_bv(0 DOWNTO 0) <= "0";
-	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
-	locked    <= sub_wire0;
-	sub_wire2    <= sub_wire1(0);
-	c0    <= sub_wire2;
-	sub_wire3    <= inclk0;
-	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 125,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 228,
-		clk0_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 20000,
-		intended_device_family => "Cyclone IV E",
-		lpm_hint => "CBX_MODULE_PREFIX=h_clk_gen",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_USED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
-		port_clk2 => "PORT_UNUSED",
-		port_clk3 => "PORT_UNUSED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		self_reset_on_loss_lock => "ON",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire4,
-		locked => sub_wire0,
-		clk => sub_wire1
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "91.199997"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "91.20000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "h_clk_gen.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "228"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen_inst.vhd TRUE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
-
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.qsf b/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
index cea9369..7607808 100644
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
@@ -86,8 +86,8 @@ set_instance_assignment -name IO_STANDARD LVDS -to hdmi_blue
 
 
 
-set_global_assignment -name VHDL_FILE h_clk_gen.vhdl
-set_global_assignment -name VHDL_FILE a_clk_gen.vhdl
+set_global_assignment -name VHDL_FILE clk1.vhdl
+set_global_assignment -name VHDL_FILE clk2.vhdl
 set_global_assignment -name VHDL_FILE edge_det.vhdl
 set_global_assignment -name VHDL_FILE debounce.vhdl
 set_global_assignment -name VHDL_FILE synchronizer.vhdl
@@ -95,5 +95,6 @@ set_global_assignment -name VHDL_FILE video_ram.vhdl
 set_global_assignment -name VHDL_FILE lcd_driver.vhdl
 set_global_assignment -name VHDL_FILE hdmi_driver.vhdl
 set_global_assignment -name VHDL_FILE a_input.vhdl
+set_global_assignment -name VHDL_FILE a_siggen.vhdl
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
index aeb8c0b..8a07fde 100644
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
@@ -7,10 +7,10 @@ entity lcd_driver is
         clk_50m : in std_logic;
         sys_rst_n : in  std_logic;
 		
-		a_video : in std_logic;
-		a_bright : in std_logic;
-		a_hsync : in std_logic;
-		a_vsync : in std_logic;
+		s_video : in std_logic;
+		s_bright : in std_logic;
+		s_hsync : in std_logic;
+		s_vsync : in std_logic;
 		
 		hdmi_ddc_scl : inout std_logic;
 		hdmi_ddc_sda : inout std_logic;
@@ -21,6 +21,7 @@ entity lcd_driver is
 		hdmi_blue : out std_logic
 
 
+
 --		hdmi_clk_p : out std_logic;
 --		hdmi_clk_n : out std_logic;
 --		hdmi_red_p : out std_logic;
@@ -36,13 +37,30 @@ architecture behavioural of lcd_driver is
 
 	
 		signal wren :std_logic;
-      signal w_addr :std_logic_vector(17 downto 0);
+	        signal w_addr :std_logic_vector(17 downto 0);
 		signal r_addr :std_logic_vector(17 downto 0);
 		
-		signal a_clk : std_logic;
-		signal h_clk : std_logic;
-		signal h_data : std_logic_vector(1 downto 0);
+		signal clk_80m : std_logic;
+		signal clk_20m : std_logic;
+		signal clk_91_25m : std_logic;
+	
+		signal a_bright: std_logic;
+		signal a_video: std_logic;
+		signal a_hsync: std_logic;
+		signal a_vsync : std_logic;
+
+
 		signal a_data : std_logic_vector(1 downto 0);
+
+		signal f_data : std_logic_vector(1 downto 0);
+
+		signal f_red : std_logic_vector(7 downto 0);
+		signal f_green : std_logic_vector(7 downto 0);
+		signal f_blue : std_logic_vector(7 downto 0);
+		signal f_hsync:  std_logic;
+		signal f_vsync : std_logic;
+
+		signal h_data : std_logic_vector(1 downto 0);
 	
 begin
 
@@ -52,29 +70,71 @@ begin
 -- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
 
 
-   h_clk <= clk_50m;
+     clk1_0:work.clk1
+	port map (
+		areset => not sys_rst_n,
+		inclk0 => clk_50m,
+		c0 => clk_80m,
+		c1 => clk_20m
+	);
+
+
+     clk2_0:work.clk2
+	port map (
+		areset => not sys_rst_n,
+		inclk0 => clk_50m,
+		c0 => clk_91_25m
+	);
+
+
+   
+	a_siggen0:work.a_siggen 
+	port map (
+	  sys_rst_n => sys_rst_n,
+		pclk => clk_20m,
+		bright=> a_bright,
+		video => a_video,
+		hsync => a_hsync,
+		vsync => a_vsync
+	);
    
-	a_inpuut0: work.a_input
+
+
+	a_input0: work.a_input
 	port map (
 	  sys_rst_n => sys_rst_n,
-	  clk_50m => clk_50m,
+	  p_clk => clk_80m,
 	  
 	  video_in => a_video,
 	  bright_in => a_bright,
 	  hsync_in => a_hsync,
 	  vsync_in => a_vsync,
 	  
-	  p_clk_out => a_clk,
 	  video_out =>  a_data,
 	  addr_out  => w_addr,
 	  wren_out => wren
 	  );
 
+
+
+	formatter0: work.formatter
+	port map (
+	  sys_rst_n => sys_rst_n,
+	  p_clk => clk_91_25m,
+
+	  addr_out => r_addr,
+	  hsync_out => h_hsync,
+	  vsync_out => h_vsync,
+	  wren_out => wren
+	  );
+
+
+   
 	
-   process (sys_rst_n,r_addr,h_clk)  begin 
+   process (sys_rst_n,r_addr,clk_91_25m)  begin 
 		if sys_rst_n = '0' then 
 			r_addr <=(others =>'0');
-		elsif rising_edge(h_clk) then
+		elsif rising_edge(clk_91_25m) then
 		   r_addr <= std_logic_vector(unsigned(w_addr)+1);
 		end if;
 	end process;
@@ -83,21 +143,24 @@ begin
    PORT MAP (
 		data		=>a_data,
 		wraddress	=>w_addr,
-		wrclock		=>a_clk,
+		wrclock		=>clk_80m,
 		wren		=> wren,
 		
 		rdaddress => r_addr,
-		rdclock	 => h_clk,
+		rdclock	 => clk_91_25m,
 		q		=> h_data
 	);
 
+
+
+
 	
 
 	red_driver : work.hdmi_driver
 	PORT MAP (
 		in_h => h_data(0),
 		in_l => h_data(1),
-		clk => h_clk,
+		clk => clk_91_25m,
 		output => hdmi_red
 	);
  	
diff --git a/spartan6/hp_lcd_driver/.gitignore b/spartan6/hp_lcd_driver/.gitignore
new file mode 100644
index 0000000..567609b
--- /dev/null
+++ b/spartan6/hp_lcd_driver/.gitignore
@@ -0,0 +1 @@
+build/
diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile
new file mode 100644
index 0000000..d526ede
--- /dev/null
+++ b/spartan6/hp_lcd_driver/Makefile
@@ -0,0 +1,288 @@
+include relpath.mk
+
+PART=xc6slx9-2-tqg144
+TOP=hp_lcd_driver
+BUILD=build
+VSRCS=hp_lcd_driver.vhd
+UCF=hp_lcd_driver.ucf
+UT=hp_lcd_driver.ut
+IPSRCS=vram.xco
+
+DESIGN_NAME=${TOP}
+ISE_BINDIR=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64
+INTSTYLE=
+
+XST_FLAGS=${INTSTYLE}
+NGDBUILD_FLAGS=${INTSTYLE} -p ${PART} -dd _ngo -nt timestamp
+MAP_FLAGS=${INTSTYLE} -p ${PART} -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off 
+PAR_FLAGS=${INTSTYLE} -w -ol high -mt off 
+TRCE_FLAGS=${INTSTYLE} -v 3 -s 2 -n 3 -fastpaths
+BITGEN_FLAGS=${INTSTYLE} 
+
+
+
+GEN_VSRCS=${IPSRCS:%.xco=${BUILD}/%.vhd}
+BASE=${BUILD}/${DESIGN_NAME}
+XST=${BASE}.xst
+PRJ=${BASE}.prj
+SYR=${BASE}.syr
+NGC=${BASE}.ngc
+NGD=${BASE}.ngd
+MAP_NCD=${BASE}_map.ncd
+NCD=${BASE}.ncd
+PCF=${BASE}.pcf
+TWR=${BASE}.twr
+TWX=${BASE}.twx
+BIT=${BASE}.bit
+SVF=${BASE}.svf
+
+XST_TMPDIR=xst/projnav.tmp
+XST_DIR=xst
+
+
+
+default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF}
+
+clean: 
+	/bin/rm -rf ${BUILD}
+
+${PRJ}: ${VSRCS} ${GEN_VSRCS}
+	mkdir -p ${BUILD}
+	rm -f  $@
+	for file in $(GEN_VSRCS) ${VSRCS}; do \
+	echo "vhdl work $$(realpath -m --relative-to=${BUILD} $${file})" >> $@ ; \
+	done ;
+
+${NGC}:${XST}
+	(cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD}))
+
+${XST}: ${PRJ} ${DESIGN_NAME}.xst_template
+	rm -f  $@
+	echo 'set -tmpdir "${XST_TMPDIR}"' >> $@
+	echo 'set -xsthdpdir "${XST_DIR}"' >> $@
+	cat  ${DESIGN_NAME}.xst_template >> $@
+	echo "-ifn $(call relpath,${PRJ},${BUILD})" >> $@ 
+	echo "-ofn $(call relpath,${BASE},${BUILD})" >> $@ 
+	echo "-p ${PART}" >> $@
+	echo "-top ${TOP}" >> $@
+
+${NGD}:${NGC} ${UCF}
+	(cd ${BUILD} && ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD}))
+
+${MAP_NCD} ${PCF}:${NGD}
+	(cd ${BUILD} && ${ISE_BINDIR}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD})  $(call relpath,${PCF},${BUILD}))
+
+${NCD}: ${MAP_NCD} ${PCF}
+	(cd ${BUILD} && ${ISE_BINDIR}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${TWR} ${TWX}: ${NCD} ${PCF}
+	(cd ${BUILD} && ${ISE_BINDIR}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD}))
+
+${BIT}:${NCD} ${UT}
+	(cd ${BUILD} && ${ISE_BINDIR}/bitgen ${BITGEN_FLAGS} -f  $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD}))
+
+${SVF}:${BIT}
+	( cd ${BUILD} && \
+	echo -e "setMode -bs \n\
+	setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\"  \n\
+	addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\
+	program -p 1 \n\
+	quit \n" > impact.run &&\
+	${ISE_BINDIR}/impact -batch impact.run)
+
+
+${BUILD}/%.vhd:%.xco
+	mkdir -p ${BUILD}
+	(cd ${BUILD} && touch empty.prj  && ${ISE_BINDIR}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj)
+
+
+#
+#
+##
+## Flags and option values that control the behavior of the Xilinx tools.
+## You can override these values in the makefile that includes this one.
+## Otherwise, the default values will be set as shown below.
+##
+#
+## Unless otherwise specified, the name of the design and the top-level
+## entity are derived from the name of the directory that contains the design.
+#DIR_SPACES  := $(subst /, ,$(CURDIR))
+#DIR_NAME    := $(word $(words $(DIR_SPACES)), $(DIR_SPACES))
+#DESIGN_NAME ?= $(DIR_NAME)
+#TOP_NAME    ?= $(DESIGN_NAME)
+#SYNTH_DIR   ?= .
+#SIM_DIR   ?= .
+#
+## Extract the part identifier from the project .npl file.
+#PART_TYPE        ?=            $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVICE)
+#PART_SPEED_GRADE ?= $(subst -,,$(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVSPEED))
+#PART_PACKAGE     ?=            $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVPKG)
+#PART             ?= $(PART_TYPE)-$(PART_SPEED_GRADE)-$(PART_PACKAGE)
+#
+## Flags common to both FPGA design flow.
+#INTSTYLE         ?= -intstyle silent      # call Xilinx tools in silent mode
+#XST_FLAGS        ?= $(INTSTYLE)           # most synthesis flags are specified in the .xst file
+#UCF_FILE         ?= $(DESIGN_NAME).ucf    # constraint/pin-assignment file
+#NGDBUILD_FLAGS   ?= $(INTSTYLE) -dd _ngo  # ngdbuild flags
+#NGDBUILD_FLAGS += $(if $(UCF_FILE),-uc,) $(UCF_FILE)         # append the UCF file option if it is specified 
+#
+## Flags for FPGA-specific tools.  These were extracted by looking in the
+## .cmd_log file after compiling the design with the WebPACK/ISE GUI.
+#MAP_FLAGS        ?= $(INTSTYLE) -cm area -pr b -c 100 -tx off
+#PAR_FLAGS        ?= $(INTSTYLE) -w -ol std -t 1
+#TRCE_FLAGS       ?= $(INTSTYLE) -e 3 -l 3
+#BITGEN_FLAGS     ?= $(INTSTYLE) -w        # most bitgen flags are specified in the .ut file
+#PROMGEN_FLAGS    ?= -u 0                  # flags that control the MCS/EXO file generation
+#
+## Determine the version of Xilinx ISE that is being used by reading it from the
+## readme.txt file in the top-level directory of the Xilinx software.
+#PROJNAV_DIR ?= .
+#
+#XST_FPGA_OPTIONS_FILE ?= $(PROJNAV_DIR)/$(DESIGN_NAME).xst
+#BITGEN_OPTIONS_FILE   ?= $(DESIGN_NAME).ut
+#XST_OPTIONS_FILE       = $(XST_FPGA_OPTIONS_FILE)
+#
+#
+#
+##
+## The following rules describe how to compile the design to an FPGA
+##
+#
+#HDL_FILES := $(foreach file,$(SRCS_SYNTH),$(SYNTH_DIR)/$(file))
+#SIM_FILES := $(foreach file,$(SRCS_SIM),$(SIM_DIR)/$(file))
+#
+## default target
+#all: bit
+#
+#
+## cleanup the source code to make it look nice
+#%.nice: %.vhd
+#	$(EMACS) -batch $< -f vhdl-beautify-buffer -f save-buffer
+#	$(RM) $<~
+#
+##PRJ FIle generation
+#%.prj:
+#	rm -f  $(DESIGN_NAME).prj;
+#	for file in $(HDL_FILES); do \
+#	echo "vhdl work $${file}" >> $(DESIGN_NAME).prj ; \
+#	done ;
+#
+#%.ut:
+#	cp -n $(UTILITY_DIR)/default.ut $(DESIGN_NAME).ut
+#
+#%.xst:
+#	cp -n $(UTILITY_DIR)/default.xst $(DESIGN_NAME).xst
+#
+#%.ucf:
+#	cp -n $(UTILITY_DIR)/default.ucf $(UCF_FILE)
+#
+#
+#
+#
+#
+## Synthesize the HDL files into an NGC file.  This rule is triggered if
+## any of the HDL files are changed or the synthesis options are changed.
+#%.ngc: $(HDL_FILES) $(XST_OPTIONS_FILE) $(DESIGN_NAME).prj $(DESIGN_NAME).ut
+#	$(SET_OPTION_VALUES) $(XST_OPTIONS_FILE) \
+#		"set -tmpdir $(PROJNAV_DIR)" \
+#		"-lso $(DESIGN_NAME).lso" \
+#		"-ifn $(DESIGN_NAME).prj" \
+#		"-ofn $(DESIGN_NAME)" \
+#		"-p $(PART)" \
+#		"-top $(TOP_NAME)" \
+#			> $(PROJNAV_DIR)/tmp.xst
+#	${ISE_BINDIR}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr
+#
+## Take the output of the synthesizer and create the NGD file.  This rule
+## will also be triggered if constraints file is changed.
+#%.ngd: %.ngc %.ucf
+#	${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd
+#
+## Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file.
+#%_map.ncd %.pcf: %.ngd
+#	${ISE_BINDIR}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf
+#
+## Place & route the mapped NCD file to create the final NCD file.
+#%.ncd: %_map.ncd %.pcf
+#	${ISE_BINDIR}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf
+#
+## Take the final NCD file and create an FPGA bitstream file.  This rule will also be
+## triggered if the bit generation options file is changed.
+#%.bit: %.ncd $(BITGEN_OPTIONS_FILE)
+#	${ISE_BINDIR}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd
+#
+## Convert a bitstream file into an MCS hex file that can be stored into Flash memory.
+#%.mcs: %.bit
+#	${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs
+#
+## Convert a bitstream file into an EXO hex file that can be stored into Flash memory.
+#%.exo: %.bit
+#	${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p exo
+#
+## Use .config suffix to trigger creation of a bit/svf file
+## depending upon whether an FPGA is the target device.
+#%.config: %.bit ;
+#
+## Create the FPGA timing report after place & route.
+#%.twr: %.ncd %.pcf
+#	${ISE_BINDIR}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf
+#
+## Use .timing suffix to trigger timing report creation.
+#%.timing: %.twr ;
+#
+## Preserve intermediate files.
+#.PRECIOUS: %.ngc %.ngd %_map.ncd %.ncd %.twr %.vm6 %.jed %.prj %.ut %.xst %.ucf
+#
+## Clean up after creating the configuration file.
+#%.clean:
+#	-$(RM) *.stx *.ucf.untf *.mrp *.nc1 *.ngm *.prm *.lfp
+#	-$(RM) *.placed_ncd_tracker *.routed_ncd_tracker
+#	-$(RM) *.pad_txt *.twx *.log *.vhd~ *.dhp *.jhd *.cel
+#	-$(RM) *.ngr *.ngc *.ngd *.syr *.bld *.pcf
+#	-$(RM) *_map.mrp *_map.ncd *_map.ngm *.ncd *.pad *.bit
+#	-$(RM) *.par *.xpi *_pad.csv *_pad.txt *.drc *.bgn *.lso *.npl
+#	-$(RM) *.xml *_build.xml *.rpt *.gyd *.mfd *.pnx *.xrpt *.ptwx *.twr *.srp
+#	-$(RM) *.vm6 *.jed *.err *.ER result.txt tmperr.err *.bak *.vhd~
+#	-$(RM) *.zip *_backup *.*log *.map *.unroutes *.html
+#	-$(RM) impactcmd.txt tmp.xst impact.run *.wlf transcript
+#	-$(RMDIR) xst _ngo *_html __projnav xlnx_auto_* work
+#
+## Clean everything.
+#%.distclean: %.clean
+#	-$(RM) *.prj
+#
+#%.impact : $(DESIGN_NAME).bit
+#	echo -e "setMode -bs \n\
+#	setCable -p auto \n\
+#	identify  \n\
+#	assignFile -p 1 -file $(DESIGN_NAME).bit \n\
+#	program -p 1 \n\
+#	quit \n" > impact.run
+#	${ISE_BINDIR}/impact -batch impact.run
+#
+##Simulation using ModelSIM
+#setlib:
+#	${ISE_BINDIR}/vlib work
+#
+#vsim-compile: setlib $(SIM_FILES) $(HDL_FILES)
+#	${ISE_BINDIR}/vcom $(HDL_FILES)  $(SIM_FILES)
+#
+#vsim: vsim-compile
+#	${ISE_BINDIR}/vsim  $(TESTBENCH_NAME)
+#
+#vsim-run: vsim-compile
+#	${ISE_BINDIR}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME)
+#
+##
+## Default targets for FPGA compilations.
+##
+#
+#config          : $(DESIGN_NAME).config
+#bit             : $(DESIGN_NAME).bit
+#mcs             : $(DESIGN_NAME).mcs
+#exo             : $(DESIGN_NAME).exo
+#timing          : $(DESIGN_NAME).timing
+#clean           : $(DESIGN_NAME).clean
+#distclean       : $(DESIGN_NAME).distclean
+#nice            : $(subst .vhd,.nice,$(HDL_FILES))
+#impact          : $(DESIGN_NAME).impact
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
new file mode 100644
index 0000000..8e67eae
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
@@ -0,0 +1,3 @@
+NET "hdmi_r" IOSTANDARD = LVCMOS33;
+NET "hdmi_b" LOC = P67;
+
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ut b/spartan6/hp_lcd_driver/hp_lcd_driver.ut
new file mode 100644
index 0000000..ea9319f
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ut
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhd b/spartan6/hp_lcd_driver/hp_lcd_driver.vhd
new file mode 100644
index 0000000..9b7aac9
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    13:20:32 04/26/2025 
+-- Design Name: 
+-- Module Name:    hp_lcd_driver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hp_lcd_driver is
+    Port ( clk_50m : in  STD_LOGIC;
+	   sys_rst_n : in STD_LOGIC;
+           hdmi_clk : out  STD_LOGIC;
+           hdmi_r : out  STD_LOGIC;
+           hdmi_g : out  STD_LOGIC;
+           hdmi_b : out  STD_LOGIC;
+           video : in  STD_LOGIC;
+           bright : in  STD_LOGIC;
+           hsync : in  STD_LOGIC;
+           vsync : in  STD_LOGIC);
+end hp_lcd_driver;
+
+architecture Behavioral of hp_lcd_driver is
+
+signal addr : std_logic_vector(17 downto 0);
+signal dout : std_logic_vector(1 downto 0);
+signal din : std_logic_vector(1 downto 0);
+
+begin
+
+hdmi_clk <= clk_50m;
+hdmi_b<='0';
+
+din <=(video,bright);
+
+vram0: entity work.vram
+	port map (
+	clka => clk_50m,
+	wea => "1",
+	addra => addr,
+	dina => din,
+	clkb => clk_50m,
+	addrb => addr,
+	doutb => dout
+);
+
+hdmi_g <= dout(0);
+hdmi_r <= dout(1);
+
+   process (sys_rst_n,clk_50m)  begin
+                if sys_rst_n = '0' then
+                        addr <=(others =>'0');
+                elsif rising_edge(clk_50m) then
+                   addr <= std_logic_vector(unsigned(addr)+1);
+                end if;
+        end process;
+
+
+
+end Behavioral;
+
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.xst_template b/spartan6/hp_lcd_driver/hp_lcd_driver.xst_template
new file mode 100644
index 0000000..b5f39c1
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.xst_template
@@ -0,0 +1,46 @@
+run
+-ofmt NGC
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/spartan6/hp_lcd_driver/relpath.mk b/spartan6/hp_lcd_driver/relpath.mk
new file mode 100644
index 0000000..ee42901
--- /dev/null
+++ b/spartan6/hp_lcd_driver/relpath.mk
@@ -0,0 +1,35 @@
+override define \s :=
+$() $()
+endef
+
+ifndef $(\s)
+override $(\s) :=
+else
+$(error Defined special variable '$(\s)': reserved for internal use)
+endif
+
+override define dirname
+$(patsubst %/,%,$(dir $(patsubst %/,%,$1)))
+endef
+
+override define prefix_1
+$(if $(or $\
+$(patsubst $(abspath $3)%,,$(abspath $1)),$\
+$(patsubst $(abspath $3)%,,$(abspath $2))),$\
+$(strip $(call prefix_1,$1,$2,$(call dirname,$3))),$\
+$(strip $(abspath $3)))
+endef
+
+override define prefix
+$(call prefix_1,$1,$2,$1)
+endef
+
+override define relpath_1
+$(patsubst /%,%,$(subst $(\s),/,$(patsubst %,..,$(subst /,$(\s),$\
+$(patsubst $3%,%,$(abspath $2)))))$\
+$(patsubst $3%,%,$(abspath $1)))
+endef
+
+override define relpath
+$(call relpath_1,$1,$2,$(call prefix,$1,$2))
+endef
diff --git a/spartan6/hp_lcd_driver/vram.xco b/spartan6/hp_lcd_driver/vram.xco
new file mode 100644
index 0000000..f4624c4
--- /dev/null
+++ b/spartan6/hp_lcd_driver/vram.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Sat Apr 26 13:15:00 2025
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=vram
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=2
+CSET read_width_b=2
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=228096
+CSET write_width_a=2
+CSET write_width_b=2
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: 74d82cad