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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY a_input IS
generic (debounce_stages : natural := 2;
sync_stages : natural := 2;
hres : natural := 594;
front_porch : natural := 100;
p_clk_multiple : natural := 4;
vres : natural := 384);
PORT
(
p_clk : in std_logic;
sys_rst_n : in std_logic;
video_in:in std_logic;
bright_in:in std_logic;
hsync_in:in std_logic;
vsync_in: in std_logic;
video_out: out std_logic_vector(1 downto 0);
addr_out : out std_logic_vector(17 downto 0);
wren_out : out std_logic;
p_clk_out : out std_logic
);
END a_input;
ARCHITECTURE beh OF a_input IS
signal p_clk_div : natural;
signal row_addr : std_logic_vector(17 downto 0) ;
signal addr : std_logic_vector(17 downto 0) ;
signal wren: std_logic;
signal s_hsync: std_logic;
signal d_hsync: std_logic;
signal pe_hsync: std_logic;
signal ne_hsync: std_logic;
signal s_vsync: std_logic;
signal d_vsync: std_logic;
signal s_video: std_logic;
signal s_bright: std_logic;
signal fp_counter:natural;
signal active_counter:natural;
begin
video_sync: entity work.synchronizer
generic map(stages => sync_stages +debounce_stages)
port map (
clk=>p_clk,
i => video_in,
o =>s_video
);
bright_sync: entity work.synchronizer
generic map(stages => sync_stages +debounce_stages)
port map (
clk=>p_clk,
i => bright_in,
o =>s_bright
);
hsync_sync: entity work.synchronizer
generic map(stages => sync_stages)
port map (
clk=>p_clk,
i => hsync_in,
o =>s_hsync
);
vsync_sync: entity work.synchronizer
generic map(stages => sync_stages )
port map (
clk=>p_clk,
i => vsync_in,
o =>s_vsync
);
hsync_debounce : entity work.debounce
generic map(stages => debounce_stages)
port map(
clk => p_clk,
i => s_hsync,
o => d_hsync);
hsync_ed : entity work.edge_det
port map(
clk => p_clk,
sig => d_hsync,
pe => pe_hsync,
ne => ne_hsync);
vsync_debounce : entity work.debounce
generic map(stages => debounce_stages)
port map(
clk => p_clk,
i => s_vsync,
o => d_vsync);
-- horizontal state machine
process (sys_rst_n,p_clk,d_hsync,d_vsync) begin
if sys_rst_n = '0' then
row_addr<=(others =>'0');
addr<=(others =>'0');
p_clk_div<=p_clk_multiple;
active_counter <=0;
fp_counter <=0;
elsif rising_edge(p_clk) then
if d_vsync='1' then
row_addr<=(others => '0');
addr<=(others => '0');
fp_counter <= front_porch;
active_counter <=hres;
p_clk_div <=p_clk_multiple;
elsif pe_gsync ='1' then
row_addr <= std_logic_vector(unsigned(row_addr)+1);
elsif ne_hsync='1' then
fp_counter <= front_porch;
active_counter <=hres;
p_clk_div <=p_clk_multiple;
addr<=row_addr;
elsif fp_counter /= 0 then
fp_counter <= fp_counter -1;
elsif active_counter /= 0 then
if p_clk_div = 0 then
p_clk_div <=p_clk_multiple;
active_counter <= active_counter -1;
addr <= std_logic_vector(unsigned(addr)+vres);
else
p_clk_div <= p_clk_div - 1;
end if;
else
p_clk_div <=p_clk_multiple;
end if;
end if;
end process;
wren <= '1' when p_clk_div=2 else '0';
addr_out <= addr;
video_out <= (s_video, s_bright);
wren_out <= wren;
p_clk_out <= p_clk;
end beh;
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