add noddy cyclone IV fpga design

15 files changed, 1743 insertions, 0 deletions

diff --git a/smh-ac415-fpga/lcd_driver/.gitignore b/smh-ac415-fpga/lcd_driver/.gitignore
new file mode 100644
index 0000000..da1292e
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/.gitignore
@@ -0,0 +1,6 @@
+*.svf
+*.qws
+db
+incremental_db
+greybox_tmp
+output_files
diff --git a/smh-ac415-fpga/lcd_driver/Makefile b/smh-ac415-fpga/lcd_driver/Makefile
new file mode 100644
index 0000000..55c2402
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/Makefile
@@ -0,0 +1,56 @@
+PROJECT = lcd_driver
+SOURCE_FILES = lcd_driver.vhdl 
+ASSIGNMENT_FILES = lcd_driver.qpf lcd_driver.qsf 
+
+BUILD=output_files
+
+OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg
+
+MAP_ARGS = --smart 
+FIT_ARGS = 
+ASM_ARGS =
+STA_ARGS =
+CPF_ARGS = -c -q 1MHZ -g 3.3 -n p
+
+SVF=${PROJECT}.svf
+
+
+default: ${SVF}
+
+${SVF}: ${BUILD}/${PROJECT}.svf
+	cat $< > $@ || /bin/rm -f $@
+
+program: ${SVF}
+	${OPENOCD} -c "init; svf $<; exit"
+
+all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt  ${BUILD}/${PROJECT}.svf
+
+clean:
+	rm -rf db ${BUILD} *.orig *.bak incremental_db
+
+map: ${BUILD}/$(PROJECT).map.rpt
+fit: ${BUILD}/$(PROJECT).fit.rpt
+asm: ${BUILD}/$(PROJECT).asm.rpt
+sta: ${BUILD}/$(PROJECT).sta.rpt
+
+${BUILD}/$(PROJECT).map.rpt: $(SOURCE_FILES) 
+	run_quartus quartus_map $(MAP_ARGS) ${PROJECT} 
+
+${BUILD}/$(PROJECT).fit.rpt: ${BUILD}/$(PROJECT).map.rpt
+	run_quartus quartus_fit $(FIT_ARGS) $(PROJECT)
+
+${BUILD}/$(PROJECT).asm.rpt: ${BUILD}/$(PROJECT).fit.rpt
+	run_quartus quartus_asm $(ASM_ARGS) $(PROJECT)
+
+${BUILD}/$(PROJECT).sta.rpt: ${BUILD}/$(PROJECT).fit.rpt
+	run_quartus quartus_sta $(STA_ARGS) $(PROJECT) 
+
+${BUILD}/$(PROJECT).sof: ${BUILD}/$(PROJECT).asm.rpt
+
+${BUILD}/$(PROJECT).svf:  ${BUILD}/$(PROJECT).sof
+	run_quartus quartus_cpf  ${CPF_ARGS} $< $@
+
+tidy:
+	for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
+
+
diff --git a/smh-ac415-fpga/lcd_driver/a_clk_gen.vhdl b/smh-ac415-fpga/lcd_driver/a_clk_gen.vhdl
new file mode 100644
index 0000000..4918a95
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/a_clk_gen.vhdl
@@ -0,0 +1,366 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: a_clk_gen.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FIALE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web EditionA
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY a_clk_gen IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END a_clk_gen;
+
+
+ARCHITECTURE SYN OF a_clk_gen IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	locked    <= sub_wire0;
+	sub_wire2    <= sub_wire1(0);
+	c0    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 8,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone IV E",
+		lpm_hint => "CBX_MODULE_PREFIX=a_clk_gen",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire4,
+		locked => sub_wire0,
+		clk => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "a_clk_gen.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL a_clk_gen_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
+
diff --git a/smh-ac415-fpga/lcd_driver/a_input.vhdl b/smh-ac415-fpga/lcd_driver/a_input.vhdl
new file mode 100644
index 0000000..15f1990
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/a_input.vhdl
@@ -0,0 +1,173 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY a_input IS
+    generic (debounce_stages : natural := 2;
+             sync_stages     : natural := 2;
+	     hres	     : natural := 594;
+             front_porch     : natural := 100;
+	     p_clk_multiple  : natural := 4;
+	     vres            : natural := 384);
+
+	PORT
+	(
+	  clk_50m : in std_logic;
+	  sys_rst_n : in std_logic;
+	  video_in:in std_logic;
+	  bright_in:in std_logic;
+	  hsync_in:in std_logic;
+	  vsync_in: in std_logic;
+	  video_out: out std_logic_vector(1 downto 0);
+	  addr_out : out std_logic_vector(17 downto 0);
+	  wren_out : out std_logic;
+	  p_clk_out : out std_logic
+	  );
+	  
+END a_input;
+
+
+ARCHITECTURE beh OF a_input IS
+
+   signal p_clk : std_logic;
+   signal p_clk_div : natural;
+   signal addr : std_logic_vector(17 downto 0)	;
+   signal wren: std_logic;
+
+
+ signal s_hsync: std_logic;
+ signal d_hsync: std_logic;
+ signal ne_hsync: std_logic;
+
+
+ signal s_vsync: std_logic;
+ signal d_vsync: std_logic;
+
+ signal s_video: std_logic;
+ signal s_bright: std_logic;
+
+ signal fp_counter:natural;
+ signal active_counter:natural;
+
+		
+begin
+
+
+	a_clk0: work.a_clk_gen
+	port map (
+		areset		=> not sys_rst_n,
+		inclk0 		=> clk_50m,
+		c0 => p_clk
+		);
+	
+
+    video_sync: entity work.synchronizer
+		generic map(stages => sync_stages +debounce_stages)
+		port map (
+			clk=>p_clk,
+			i => video_in,
+			o =>s_video
+			);
+
+
+
+    bright_sync: entity work.synchronizer
+		generic map(stages => sync_stages +debounce_stages)
+		port map (
+			clk=>p_clk,
+			i => bright_in,
+			o =>s_bright
+			);
+
+
+    hsync_sync: entity work.synchronizer
+		generic map(stages => sync_stages)
+		port map (
+			clk=>p_clk,
+			i => hsync_in,
+			o =>s_hsync
+			);
+
+
+
+    vsync_sync: entity work.synchronizer
+		generic map(stages => sync_stages  )
+		port map (
+			clk=>p_clk,
+			i => vsync_in,
+			o =>s_vsync
+			);
+
+    hsync_debounce : entity work.debounce
+        generic map(stages => debounce_stages)
+        port map(
+            clk => p_clk,
+            i   => s_hsync,
+            o   => d_hsync);
+
+
+    hsync_ed : entity work.edge_det
+        port map(
+            clk => p_clk,
+            sig => d_hsync,
+            ne  => ne_hsync);
+
+
+
+
+    vsync_debounce : entity work.debounce
+        generic map(stages => debounce_stages)
+        port map(
+            clk => p_clk,
+            i   => s_vsync,
+            o   => d_vsync);
+
+
+
+-- horizontal state machine
+
+	process (sys_rst_n,p_clk,d_hsync,d_vsync)  begin
+	if sys_rst_n = '0' then
+		addr<=(others =>'0');
+		p_clk_div<=p_clk_multiple;
+		active_counter <=0;
+		fp_counter <=0;
+	elsif rising_edge(p_clk) then
+		if d_vsync='1' then
+			addr<=(others => '0');
+			fp_counter <= front_porch;
+			active_counter <=hres;
+			p_clk_div <=p_clk_multiple;
+		elsif ne_hsync='1' then
+			fp_counter <= front_porch;
+			active_counter <=hres;
+			p_clk_div <=p_clk_multiple;
+			addr <= std_logic_vector(unsigned(addr)+1);
+		elsif fp_counter /= 0 then
+			fp_counter <= fp_counter -1;
+		elsif active_counter /= 0 then	
+			if p_clk_div = 0 then
+				p_clk_div <=p_clk_multiple;
+				active_counter <= active_counter  -1;
+		   		addr <= std_logic_vector(unsigned(addr)+vres);
+			else 
+				p_clk_div <= p_clk_div - 1;
+			end if;
+		end if;
+	end if;
+	end process;
+			
+
+        wren <= '1' when p_clk_div=2 else '0';
+
+	addr_out <= addr;
+        video_out <= (s_video, s_bright);
+        wren_out <= wren;
+
+        p_clk_out <= p_clk;
+
+
+end beh;
diff --git a/smh-ac415-fpga/lcd_driver/ddio_out.vhdl b/smh-ac415-fpga/lcd_driver/ddio_out.vhdl
new file mode 100644
index 0000000..9c634f4
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/ddio_out.vhdl
@@ -0,0 +1,111 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: ALTDDIO_OUT 
+
+-- ============================================================
+-- File Name: ddio_out.vhd
+-- Megafunction Name(s):
+-- 			ALTDDIO_OUT
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY ddio_out IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+END ddio_out;
+
+
+ARCHITECTURE SYN OF ddio_out IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+BEGIN
+	dataout    <= sub_wire0(0 DOWNTO 0);
+
+	ALTDDIO_OUT_component : ALTDDIO_OUT
+	GENERIC MAP (
+		extend_oe_disable => "OFF",
+		intended_device_family => "Cyclone IV E",
+		invert_output => "OFF",
+		lpm_hint => "UNUSED",
+		lpm_type => "altddio_out",
+		oe_reg => "UNREGISTERED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		datain_h => datain_h,
+		datain_l => datain_l,
+		outclock => outclock,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
+-- Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
+-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
+-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.qip TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.bsf TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_inst.vhd TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.inc TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.cmp TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.ppf TRUE FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+
diff --git a/smh-ac415-fpga/lcd_driver/debounce.vhdl b/smh-ac415-fpga/lcd_driver/debounce.vhdl
new file mode 100644
index 0000000..654a2f3
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/debounce.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity debounce is
+    generic (stages : natural := 1);
+    port (clk : in  std_logic;
+          i   : in  std_logic;
+          o   : out std_logic);
+end debounce;
+
+architecture Behavioral of debounce is
+    signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
+    constant zero    : std_logic_vector(stages-1 downto 0) := (others => '0');
+    constant one     : std_logic_vector(stages-1 downto 0) := (others => '1');
+    signal output    : std_logic                           := '0';
+begin
+
+    o <= output;
+
+    process (clk,flipflops,i)
+    begin
+        if rising_edge(clk) then
+            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+            if flipflops = one and i = '1' then
+                output <= '1';
+            elsif flipflops = zero and i = '0' then
+                output <= '0';
+            end if;
+        end if;
+    end process;
+
+end architecture;
diff --git a/smh-ac415-fpga/lcd_driver/edge_det.vhdl b/smh-ac415-fpga/lcd_driver/edge_det.vhdl
new file mode 100644
index 0000000..8cb38eb
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/edge_det.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity edge_det is
+    port (clk : in  std_logic;
+          sig : in  std_logic;
+          pe  : out std_logic;
+          ne  : out std_logic;
+          e   : out std_logic
+          );
+end edge_det;
+
+architecture Behavioral of edge_det is
+    signal last : std_logic := '0';
+begin
+
+    process(clk,last,sig) 
+    begin
+        if rising_edge(clk) then
+            last <= sig;
+        end if;
+    end process;
+
+    pe <= '1' when sig = '1' and last = '0' else '0';
+    ne <= '1' when sig = '0' and last = '1' else '0';
+
+    e <= sig xor last;
+end Behavioral;
diff --git a/smh-ac415-fpga/lcd_driver/h_clk_gen.vhdl b/smh-ac415-fpga/lcd_driver/h_clk_gen.vhdl
new file mode 100644
index 0000000..05c08f4
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/h_clk_gen.vhdl
@@ -0,0 +1,366 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: h_clk_gen.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY h_clk_gen IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END h_clk_gen;
+
+
+ARCHITECTURE SYN OF h_clk_gen IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	locked    <= sub_wire0;
+	sub_wire2    <= sub_wire1(0);
+	c0    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 125,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 228,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone IV E",
+		lpm_hint => "CBX_MODULE_PREFIX=h_clk_gen",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire4,
+		locked => sub_wire0,
+		clk => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "91.199997"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "91.20000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "h_clk_gen.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "228"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL h_clk_gen_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
+
diff --git a/smh-ac415-fpga/lcd_driver/hdmi_driver.vhdl b/smh-ac415-fpga/lcd_driver/hdmi_driver.vhdl
new file mode 100644
index 0000000..7c6b422
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/hdmi_driver.vhdl
@@ -0,0 +1,52 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY hdmi_driver IS
+	PORT
+	(
+		in_h		: in std_logic;
+		in_l		: in std_logic;
+		clk	   	: in std_logic;
+		output		: out std_logic
+	);
+END hdmi_driver;
+
+
+ARCHITECTURE beh OF hdmi_driver IS
+
+   signal out_v   : std_logic_vector(0 downto 0);
+	signal out_n_v   : std_logic_vector(0 downto 0);
+	signal in_l_v   : std_logic_vector(0 downto 0);
+	signal in_h_v   : std_logic_vector(0 downto 0);
+	
+BEGIN
+	
+	output <= out_v(0);
+	in_l_v(0) <= in_l;
+	in_h_v(0) <= in_h;
+	
+	ddio_p : ALTDDIO_OUT
+	GENERIC MAP (
+		extend_oe_disable => "OFF",
+		intended_device_family => "Cyclone IV E",
+		invert_output => "OFF",
+		lpm_hint => "UNUSED",
+		lpm_type => "altddio_out",
+		oe_reg => "UNREGISTERED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		datain_h => in_h_v,
+		datain_l => in_l_v,
+		outclock => clk,
+		dataout => out_v
+	);
+
+
+END beh;
+
+
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.qpf b/smh-ac415-fpga/lcd_driver/lcd_driver.qpf
new file mode 100644
index 0000000..fbfca6e
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 11:47:00  April 20, 2025
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "11:47:00  April 20, 2025"
+
+# Revisions
+
+PROJECT_REVISION = "lcd_driver"
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.qsf b/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
new file mode 100644
index 0000000..cea9369
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
@@ -0,0 +1,99 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 11:47:00  April 20, 2025
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		lcd_driver_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE15F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY lcd_driver
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00  APRIL 20, 2025"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+
+
+set_location_assignment PIN_T22 -to clk_50m
+set_location_assignment PIN_U20 -to sys_rst_n
+
+
+set_location_assignment PIN_H22 -to hdmi_clk_n
+set_location_assignment PIN_H21 -to hdmi_clk_p
+
+#set_location_assignment PIN_F22 -to hdmi_red_n
+#set_location_assignment PIN_E22 -to hdmi_green_n
+#set_location_assignment PIN_D22 -to hdmi_blue_n
+
+set_location_assignment PIN_F21 -to hdmi_red
+set_location_assignment PIN_E21 -to hdmi_green
+set_location_assignment PIN_D21 -to hdmi_blue
+
+
+set_location_assignment PIN_N22 -to hdmi_ddc_scl
+set_location_assignment PIN_R22 -to hdmi_ddc_sda
+
+
+
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_red
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_green
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_blue
+
+
+
+
+set_global_assignment -name VHDL_FILE h_clk_gen.vhdl
+set_global_assignment -name VHDL_FILE a_clk_gen.vhdl
+set_global_assignment -name VHDL_FILE edge_det.vhdl
+set_global_assignment -name VHDL_FILE debounce.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE video_ram.vhdl
+set_global_assignment -name VHDL_FILE lcd_driver.vhdl
+set_global_assignment -name VHDL_FILE hdmi_driver.vhdl
+set_global_assignment -name VHDL_FILE a_input.vhdl
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
new file mode 100644
index 0000000..aeb8c0b
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
@@ -0,0 +1,106 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity lcd_driver is
+     port (
+        clk_50m : in std_logic;
+        sys_rst_n : in  std_logic;
+		
+		a_video : in std_logic;
+		a_bright : in std_logic;
+		a_hsync : in std_logic;
+		a_vsync : in std_logic;
+		
+		hdmi_ddc_scl : inout std_logic;
+		hdmi_ddc_sda : inout std_logic;
+
+		hdmi_clk : out std_logic;
+		hdmi_red : out std_logic;
+		hdmi_green : out std_logic;
+		hdmi_blue : out std_logic
+
+
+--		hdmi_clk_p : out std_logic;
+--		hdmi_clk_n : out std_logic;
+--		hdmi_red_p : out std_logic;
+--		hdmi_red_n : out std_logic;
+--		hdmi_green_p : out std_logic;
+--		hdmi_green_n : out std_logic;
+--		hdmi_blue_p : out std_logic;
+--		hdmi_blue_n : out std_logic
+ );
+end entity lcd_driver;
+
+architecture behavioural of lcd_driver is
+
+	
+		signal wren :std_logic;
+      signal w_addr :std_logic_vector(17 downto 0);
+		signal r_addr :std_logic_vector(17 downto 0);
+		
+		signal a_clk : std_logic;
+		signal h_clk : std_logic;
+		signal h_data : std_logic_vector(1 downto 0);
+		signal a_data : std_logic_vector(1 downto 0);
+	
+begin
+
+
+-- gtf at 30Hz   xrandr --newmode "$M" 127.98  1536 1632 1792 2048  2048 2049 2052 2083  -HSync +Vsync
+-- works at 60Hz xrandr --newmode "$M" 213.06  1536 1544 1552 1728  2048 2049 2051 2055  -HSync +Vsync
+-- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
+
+
+   h_clk <= clk_50m;
+   
+	a_inpuut0: work.a_input
+	port map (
+	  sys_rst_n => sys_rst_n,
+	  clk_50m => clk_50m,
+	  
+	  video_in => a_video,
+	  bright_in => a_bright,
+	  hsync_in => a_hsync,
+	  vsync_in => a_vsync,
+	  
+	  p_clk_out => a_clk,
+	  video_out =>  a_data,
+	  addr_out  => w_addr,
+	  wren_out => wren
+	  );
+
+	
+   process (sys_rst_n,r_addr,h_clk)  begin 
+		if sys_rst_n = '0' then 
+			r_addr <=(others =>'0');
+		elsif rising_edge(h_clk) then
+		   r_addr <= std_logic_vector(unsigned(w_addr)+1);
+		end if;
+	end process;
+	
+   vram: work.video_ram
+   PORT MAP (
+		data		=>a_data,
+		wraddress	=>w_addr,
+		wrclock		=>a_clk,
+		wren		=> wren,
+		
+		rdaddress => r_addr,
+		rdclock	 => h_clk,
+		q		=> h_data
+	);
+
+	
+
+	red_driver : work.hdmi_driver
+	PORT MAP (
+		in_h => h_data(0),
+		in_l => h_data(1),
+		clk => h_clk,
+		output => hdmi_red
+	);
+ 	
+	
+	
+end behavioural;
diff --git a/smh-ac415-fpga/lcd_driver/scripts/vhdl-pretty b/smh-ac415-fpga/lcd_driver/scripts/vhdl-pretty
new file mode 100755
index 0000000..c514b85
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/scripts/vhdl-pretty
@@ -0,0 +1,60 @@
+#! /bin/sh
+":"; exec emacs --no-site-file --script "$0" -- "$0" "$@" # -*-emacs-lisp-*-
+; vim: noai:ts=4:sw=4:syntax=lisp
+
+(setq arg0 (file-truename (car (cdr argv))))
+(setq args (cdr (cdr argv)))
+(setq argv nil)
+
+; Parse the command line arguments,
+;  --xxx           -> ("xxx" t)
+;  --no-xxx        -> ("xxx" nil)
+;  --xxx=123       -> ("xxx" 123)
+;  --xxx=abc       -> ("xxx" "abc")
+;  --xxx='abc 123' -> ("xxx" "abc 123")
+;  --xxx=abc=123   -> ("xxx" "abc=123")
+(setq args
+  (mapcar
+    (lambda (arg)
+      (cond
+        ((string-match "^--no-\\([^=]*\\)$" arg)
+          (list (intern (match-string 1 arg)) nil))
+        ((string-match "^--\\([^=]*\\)$" arg)
+          (list (intern (match-string 1 arg)) t))
+        ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\([0-9]+\\)\\2$" arg)
+          (list (intern (match-string 1 arg)) (string-to-number (match-string 3 arg))))
+        ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\(.+?\\)\\2$" arg)
+          (list (intern (match-string 1 arg)) (match-string 3 arg)))
+        (t nil)
+      ))
+    args))
+
+; Read stdin into buffer
+(defun insert-standard-input ()
+  "insert contents from standard input"
+  (condition-case nil
+      (let (line)
+        (while (setq line (read-from-minibuffer ""))
+          (insert line "\n")))
+    (error nil)))
+
+(insert-standard-input)
+(goto-char (point-min))
+
+; Load library
+(setq basedir (concat (file-name-directory arg0) "vhdl-mode"))
+(setq load-path (cons basedir load-path))
+(load-library "vhdl-mode")
+
+; Default customisation
+(vhdl-set-style "IEEE")
+
+; Customisation from cmdline
+(mapc (lambda (arg) (customize-set-variable (car arg) (car (cdr arg)))) args)
+
+; Turn on mode and beautify
+(vhdl-mode)
+(vhdl-beautify-region (point-min) (point-max))
+
+; Output buffer to stdout
+(princ (buffer-string))
diff --git a/smh-ac415-fpga/lcd_driver/synchronizer.vhdl b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl
new file mode 100644
index 0000000..99618b9
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity synchronizer is
+    generic (stages : natural := 2);
+    port (clk : in  std_logic;
+          i   : in  std_logic;
+          o   : out std_logic);
+end synchronizer;
+
+architecture Behavioral of synchronizer is
+    signal flipflops                 : std_logic_vector(stages-1 downto 0) := (others => '0');
+    attribute ASYNC_REG              : string;
+    attribute ASYNC_REG of flipflops : signal is "true";
+begin
+
+    o <= flipflops(flipflops'high);
+
+    clk_proc : process(clk,flipflops,i)
+    begin
+        if rising_edge(clk) then
+            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+        end if;
+    end process;
+
+end Behavioral;
diff --git a/smh-ac415-fpga/lcd_driver/video_ram.vhdl b/smh-ac415-fpga/lcd_driver/video_ram.vhdl
new file mode 100644
index 0000000..43bacaa
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/video_ram.vhdl
@@ -0,0 +1,232 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: video_ram.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY video_ram IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		rdclock		: IN STD_LOGIC ;
+		wraddress		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		wrclock		: IN STD_LOGIC  := '1';
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+END video_ram;
+
+
+ARCHITECTURE SYN OF video_ram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_b		: STRING;
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+			clock1	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_b => "NONE",
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		intended_device_family => "Cyclone IV E",
+		lpm_type => "altsyncram",
+		numwords_a => 206712,
+		numwords_b => 206712,
+		operation_mode => "DUAL_PORT",
+		outdata_aclr_b => "NONE",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 18,
+		widthad_b => 18,
+		width_a => 2,
+		width_b => 2,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => wraddress,
+		clock0 => wrclock,
+		data_a => data,
+		wren_a => wren,
+		address_b => rdaddress,
+		clock1 => rdclock,
+		q_b => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "413424"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "2"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "2"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "2"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "2"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "206712"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "206712"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "2"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "2"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
+-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 18 0 INPUT NODEFVAL "rdaddress[17..0]"
+-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+-- Retrieval info: USED_PORT: wraddress 0 0 18 0 INPUT NODEFVAL "wraddress[17..0]"
+-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 18 0 wraddress 0 0 18 0
+-- Retrieval info: CONNECT: @address_b 0 0 18 0 rdaddress 0 0 18 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 2 0 data 0 0 2 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 2 0 @q_b 0 0 2 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf