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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 11:47:00 April 20, 2025
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# lcd_driver_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE15F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY lcd_driver
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00 APRIL 20, 2025"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+
+
+set_location_assignment PIN_T22 -to clk_50m
+set_location_assignment PIN_U20 -to sys_rst_n
+
+
+set_location_assignment PIN_H22 -to hdmi_clk_n
+set_location_assignment PIN_H21 -to hdmi_clk_p
+
+#set_location_assignment PIN_F22 -to hdmi_red_n
+#set_location_assignment PIN_E22 -to hdmi_green_n
+#set_location_assignment PIN_D22 -to hdmi_blue_n
+
+set_location_assignment PIN_F21 -to hdmi_red
+set_location_assignment PIN_E21 -to hdmi_green
+set_location_assignment PIN_D21 -to hdmi_blue
+
+
+set_location_assignment PIN_N22 -to hdmi_ddc_scl
+set_location_assignment PIN_R22 -to hdmi_ddc_sda
+
+
+
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_red
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_green
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_blue
+
+
+
+
+set_global_assignment -name VHDL_FILE h_clk_gen.vhdl
+set_global_assignment -name VHDL_FILE a_clk_gen.vhdl
+set_global_assignment -name VHDL_FILE edge_det.vhdl
+set_global_assignment -name VHDL_FILE debounce.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE video_ram.vhdl
+set_global_assignment -name VHDL_FILE lcd_driver.vhdl
+set_global_assignment -name VHDL_FILE hdmi_driver.vhdl
+set_global_assignment -name VHDL_FILE a_input.vhdl
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file