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* xen: arm: Emacs style fixWei Liu2013-10-161-1/+1
| | | | | Signed-off-by: Wei Liu <wei.liu2@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Fixing clear_guest_offset macroJaeyong Yoo2013-10-101-2/+3
| | | | | | | | Fix the the broken macro 'clear_guest_offset' in arm. Signed-off-by: Jaeyong Yoo <jaeyong.yoo@samsung.com> Reviewed-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen: Add macros MB and GBJulien Grall2013-10-081-1/+0
| | | | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Keir Fraser <keir@xen.org> CC: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
* xen: arm: move smp_init_cpus to smpboot.cIan Campbell2013-09-271-0/+1
| | | | | | | Seems like a better home. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen: arm: use symbolic names for MPIDR bits.Ian Campbell2013-09-271-4/+6
| | | | | | | | arm32 already uses MPIDR_HWID_MASK, use it on arm64 too. Add MPIDR_{SMP,UP} (and bitwise equivalents) and use them. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen: arm: rewrite start of day page table and cpu bring upIan Campbell2013-09-274-32/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is unfortunately a rather large monolithic patch. Rather than bringing up all CPUs in lockstep as we setup paging and relocate Xen instead create a simplified set of dedicated boot time pagetables. This allows secondary CPUs to remain powered down or in the firmware until we actually want to enable them. The bringup is now done later on in C and can be driven by DT etc. I have included code for the vexpress platform, but other platforms will need to be added. The mechanism for deciding how to bring up a CPU differs between arm32 and arm64. On arm32 it is essentially a per-platform property, with the exception of PSCI which can be implemented globally (but isn't here). On arm64 there is a per-cpu property in the device tree. Secondary CPUs are brought up directly into the relocated Xen image, instead of relying on being able to launch on the unrelocated Xen and hoping that it hasn't been clobbered. As part of this change drop support for switching from secure mode to NS HYP as well as the early CPU kick. Xen now requires that it is launched in NS HYP mode and that firmware configure things such that secondary CPUs can be woken up by a primarly CPU in HYP mode. This may require fixes to bootloaders or the use of a boot wrapper. The changes done here (re)exposed an issue with relocating Xen and the compiler spilling values to the stack between the copy and the actual switch to the relocaed copy of Xen in setup_pagetables. Therefore switch to doing the copy and switch in a single asm function where we can control precisely what gets spilled to the stack etc. Since we now have a separate set of boot pagetables it is much easier to build the real Xen pagetables inplace before relocating rather than the more complex approach of rewriting the pagetables in the relocated copy before switching. This will also enable Xen to be loaded above the 4GB boundary on 64-bit. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen: arm: implement arch/platform SMP and CPU initialisation frameworkIan Campbell2013-09-272-0/+18
| | | | | | | | | | | | Includes an implementation for vexpress using the sysflags interface and support for the ARMv8 "spin-table" method. Unused until "rewrite start of day page table and cpu bring up", split out to simplify review. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen/arm: rename boot misc region to boot reloc now it has a single purposeIan Campbell2013-09-261-5/+2
| | | | | | Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm: Support dtb /memreserve/ regionsIan Campbell2013-09-262-3/+6
| | | | | | | | | | | | | This requires a mapping of the DTB during setup_mm. Previously this was in the BOOT_MISC slot, which is clobbered by setup_pagetables. Split it out into its own slot which can be preserved. Also handle these regions as part of consider_modules() and when adding pages to the heaps to ensure we do not locate any part of Xen or the heaps over them. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm: DOMHEAP_SECOND_PAGES is arm32 specificIan Campbell2013-09-261-3/+3
| | | | | | | | since 5263507b1b4a "xen: arm: Use a direct mapping of RAM on arm64" Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm: Use the hardware ID to boot correctly secondary cpusJulien Grall2013-09-261-0/+2
| | | | | | | | | Secondary CPUs will spin in head.S until their MPIDR[23:0] correspond to the smp_up_cpu. Actually Xen will set the value with the logical CPU ID which is wrong. Use the cpu_logical_map to get the correct CPU ID. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Dissociate logical and hardware CPU IDJulien Grall2013-09-261-0/+4
| | | | | | | | | | | Introduce cpu_logical_map to associate a logical CPU ID to an hardware CPU ID. This map will be filled during Xen boot via the device tree. Each CPU node contains a "reg" property which contains the hardware ID (ie MPIDR[0:23]). Also move /cpus parsing later so we can use the dt_* API. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: use cpumask_t to describe cpu mask in gic_route_dt_irqJulien Grall2013-09-261-1/+2
| | | | | | | Replace by cpumask_t to take advantage of cpumask_* helpers. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Introduce init_info structureJulien Grall2013-09-261-0/+6
| | | | | | | | This structure will gather all information to boot a secondary cpus. For now it just contains the initial stack. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Support Cortex-A7 GICIan Campbell2013-09-211-1/+2
| | | | | Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen/arm: replace io{read,write}{l,b} with {read,write}{l,b}Ian Campbell2013-09-214-29/+153
| | | | | | | | | | | | | | | | | | | | We appear to have invented the io versions ourselves for Xen on ARM, while x86 has the plain read/write. (and so does Linux FWIW) read/write are used in common driver code (specifically ns16550) so instead of keeping our own variant around lets replace it with the more standard ones. At the same time resync with Linux making the "based on" comment in both sets of io.h somewhat true (they don't look to have been very based on before...). Our io.h is now consistent with Linux v3.11. Note that iowrite and write take their arguments in the opposite order. Also make asm-arm/io.h useful and include it where necessary instead of picking up the include from mm.h. Remove the include from mm.h Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen: arm: improve VMID allocation.Ian Campbell2013-09-211-0/+3
| | | | | | | | | | | | The VMID field is 8 bits. Rather than allowing only up to 256 VMs per host reboot before things start "acting strange" instead maintain a simple bitmap of used VMIDs and allocate them statically to guests upon creation. This limits us to 256 concurrent VMs which is a reasonable improvement. Eventually we will want a proper scheme to allocate VMIDs on context switch. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen/arm: Add new platform specific callback device_is_blacklistJulien Grall2013-09-171-0/+7
| | | | | | | | | | | | | | | | Each platform code will list the device that must not pass-through to a guest. Theses devices are used for: power management, timer,... When theses devices are given to DOM0, it can controls the hardware and then break the whole platform. This callback is enough until we will start to care about power performance. For this purpose, we may need to extend this interface to implement per-device MMIO filtering to allow dom0 to continue to control devices which it owns which happen to share e.g. a clock controller with Xen. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/dts: dt_find_interrupt_controller: accept multiple compatible stringsJulien Grall2013-09-171-0/+2
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Use dt_device_match to avoid multiple if conditionsJulien Grall2013-09-171-0/+4
| | | | | | | | | | There is some place in Xen ARM code where multiple if conditions is used check the presence of a node or find a node. These pieces of code can be replace by an array and using proper device tree helpers. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Move __PSCI* from traps.c to the headerJulien Grall2013-09-101-0/+5
| | | | | | | These defines will be used to create the fake PSCI node in dom0 device tree. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Introduce MPIDR_HWID_MASKJulien Grall2013-09-091-0/+1
| | | | | | | | This define will be use later to retrieve the correct hardware CPU ID. Also replace hardcoded mask in arm32/head.S by this define. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* pl011: preserve RTS and DTR signal on UART initAndre Przywara2013-09-031-0/+4
| | | | | | | | | | | | | Although we do not support hardware flow control in the Xen driver for the PL011 UART, the other end may be configured to use it. In this case it waits in vain for the RTS signal to be asserted by the host and will never transmit any characters. So we leave RTS and DTR as they had been setup before. This fixes the UART input on Calxeda Midway, which uses hardware flow control for the serial-over-LAN functionality. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: add lower-bound check in mfn_validJaeyong Yoo2013-08-271-1/+1
| | | | | | | | | mfn_valid only checks the upper-bound of mfn (max_page). Add the lower-bound check of mfn (frametable_base_mfn). Signed-off-by: Jaeyong Yoo <jaeyong.yoo@samsung.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.grall@linaro.org>
* xen/arm: Introduce and use GLOBAL() in asm code.Andrew Cooper2013-08-271-0/+3
| | | | | Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* un-alias cpumask_any() from cpumask_first()Jan Beulich2013-08-232-0/+20
| | | | | | | | | | | | | | | | | | In order to achieve more symmetric distribution of certain things, cpumask_any() shouldn't always pick the first CPU (which frequently will end up being CPU0). To facilitate that, introduce a library-like function to obtain random numbers. The per-architecture function is supposed to return zero if no valid random number can be obtained (implying that if occasionally zero got produced as random number, it wouldn't be considered such). As fallback this uses the trivial algorithm from the C standard, extended to produce "unsigned int" results. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Reviewed-by: George Dunlap <george.dunlap@eu.citrix.com>
* xen: arm: retry trylock if strex fails on free lock.Ian Campbell2013-08-222-12/+16
| | | | | | | | | | | | | | | | | | | | | | | This comes from the Linux patches 15e7e5c1ebf5 for arm32 and 4ecf7ccb1973 for arm64 by Will Deacon and Catalin Marinas respectively. The Linux commit message says: An exclusive store instruction may fail for reasons other than lock contention (e.g. a cache eviction during the critical section) so, in line with other architectures using similar exclusive instructions (alpha, mips, powerpc), retry the trylock operation if the lock appears to be free but the strex reported failure. I have observed this due to register_cpu_notifier containing: if ( !spin_trylock(&cpu_add_remove_lock) ) BUG(); /* Should never fail as we are called only during boot. */ which was spuriously failing. The ARMv8 variant is taken directly from the Linux patch. For v7 I had to reimplement since we don't currently use ticket locks. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm64: resync atomics and spinlock asm with LinuxIan Campbell2013-08-223-94/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | This picks up the changes from Linux commit 3a0310eb369a: arm64: atomics: fix grossly inconsistent asm constraints for exclusives Our uses of inline asm constraints for atomic operations are fairly wild and varied. We basically need to guarantee the following: 1. Any instructions with barrier implications (load-acquire/store-release) have a "memory" clobber 2. When performing exclusive accesses, the addresing mode is generated using the "Q" constraint 3. Atomic blocks which use the condition flags, have a "cc" clobber This patch addresses these concerns which, as well as fixing the semantics of the code, stops GCC complaining about impossible asm constraints. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm64: Assembly optimized bitops from LinuxIan Campbell2013-08-221-195/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch replaces the previous hashed lock implementaiton of bitops with assembly optimized ones taken from Linux v3.10-rc4. The Linux derived ASM only supports 8 byte aligned bitmaps (which under Linux are unsigned long * rather than our void *). We do have actually uses of 4 byte alignment (i.e. the bitmaps in struct xmem_pool) which trigger alignment faults. Therefore adjust the assembly to work in 4 byte increments, which involved: - bit offset now bits 4:0 => mask #31 not #63 - use wN register not xN for load/modify/store loop. There is no need to adjust the shift used to calculate the word offset, the difference is already acounted for in the #63->#31 change. NB: Xen's build system cannot cope with the change from .c to .S file, remove xen/arch/arm/arm64/lib/.bitops.o.d or clean your build tree. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen/arm: Specific mapping for dom0 on OMAP5 platformChen Baozi2013-08-221-0/+4
| | | | | Signed-off-by: Chen Baozi <baozich@gmail.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen/arm: Platform recognition and initialize arch_timer for the OMAP5Chen Baozi2013-08-221-0/+25
| | | | | Signed-off-by: Chen Baozi <baozich@gmail.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen: arm: Use a direct mapping of RAM on arm64Ian Campbell2013-08-202-24/+88
| | | | | | | | | | | | We have plenty of virtual address space so we can avoid needing to map and unmap pages all the time. A totally arbitrarily chosen 32GB frame table leads to support for 5TB of RAM. I haven't tested with anything near that amount of RAM though. There is plenty of room to expand further when that becomes necessary. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* xen: gate split heap code on its own config option rather than !X86Ian Campbell2013-08-201-0/+1
| | | | | | | | | I'm going to want to disable this for 64 bit ARM. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Keir Fraser <keir@xen.org>
* xen: arm: allow virt_to_maddr to take either a pointer or an integerIan Campbell2013-08-201-3/+4
| | | | | | | | | | | | | This seems to be expected by common code which passes both pointers and unsigned long as virtual addresses. The latter case in particular is in init_node_heap() under a DIRECTMAP_VIRT_END #ifdef, which is why it hasn't affected us yet (but will in a subsequent patch). The new prototypes match the x86 versions apart from using vaddr_t instead of unsigned long. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* xen: arm: fix is_xen_fixed_mfnIan Campbell2013-08-201-1/+3
| | | | | | | | | | | The current implementation is nonsense since the xenheap and the xen text/data/etc mappings are nowhere near each other. This is only actually used by the page offlining code, which isn't active on ARM. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* xen: arm: Rename page table "hint" field to slightly more descriptive "contig"Ian Campbell2013-08-201-2/+2
| | | | | Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* xen: arm: Add zeroeth level page table macros and definesIan Campbell2013-08-201-4/+15
| | | | | Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
* xen: arm: Use _AC macros in config.hIan Campbell2013-08-201-8/+10
| | | | | Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* xen: remove evtchn_upcall_mask from interface on ARMIan Campbell2013-08-201-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | On ARM event-channel upcalls are masked using the hardware's interrupt mask bit and not by a software bit. Leaving this field present in the interface has caused some confusion already and is liable to mean it gets inadvertently used in the future. So arrange for this field to be turned into a padding field on ARM by introducing a XEN_HAVE_PV_UPCALL_MASK define. This bit is also unused for x86 PV-on-HVM guests, but we can't realistically distinguish those from x86 PV guests in the headers. Add a per-arch vcpu_event_delivery_is_enabled function to replace an open coded use of evtchn_upcall_mask in common code (in a debug keyhandler). The existing local_event_delivery_is_enabled, which operates only on current, was unimplemented on ARM and unused on x86, so remove it. ifdef the use of evtchn_upcall_mask when setting up a new vcpu info page. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
* ARM: add Calxeda Midway platformAndre Przywara2013-08-201-0/+21
| | | | | | | | | | Calxeda Midway is an ARMv7 server platform with Cortex-A15 cores. The peripheral side has many similarities with the machine known as Highbank. Add Calxeda Midway to the list of supported platforms to avoid a warning on boot and provide the proper reset method. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* xen/arm: erratum 766422: decode thumb store during data abortJulien Grall2013-08-202-0/+6
| | | | | | | | | | | | | | | | | | | | | From the errata document: When a non-secure non-hypervisor memory operation instruction generates a stage2 page table translation fault, a trap to the hypervisor will be triggered. For an architecturally defined subset of instructions, the Hypervisor Syndrome Register (HSR) will have the Instruction Syndrome Valid (ISV) bit set to 1’b1, and the Rt field should reflect the source register (for stores) or destination register for loads. On Cortex-A15, for Thumb and ThumbEE stores, the Rt value may be incorrect and should not be used, even if the ISV bit is set. All loads, and all ARM instruction set loads and stores, will have the correct Rt value if the ISV bit is set. To avoid this issue, Xen needs to decode thumb store instruction and update the transfer register. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* cleanup unused request{_dt,}_irq() parameterAndrew Cooper2013-08-081-2/+1
| | | | | | | | | The irqflags parameter appears to be an unused vestigial parameter right from the integration of the IOMMU code in 2007. The parameter is 0 at all callsites and never used. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Ian Campbell <Ian.Campbell@citrix.com>
* exynos4210: Implement vuart_info callbackJulien Grall2013-08-081-0/+1
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* exynos4210: rename UTRSTAT_TX_EMPTY in UTRSTAT_TXFEJulien Grall2013-08-081-1/+1
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* xen/arm: Implement a virtual UARTJulien Grall2013-08-081-6/+8
| | | | | | | | | | | | | | | | | This code is based on the previous vuart0 implementation. Unlike the latter, it's intend to replace UART stolen by XEN to DOM0 via dtuart=... on its command line. It's useful when the kernel is compiled with early printk enabled or for a single platform. Most of the time, the hardcoded code to handle the UART will need 2 registers: status and data, the others registers can be implemented as RAZ/WI. This commit will also drop support of early printk (based on vexpress pl011) in the guest. Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* xen/arm: Use define instead of hardcoded value in debug-pl011Julien Grall2013-08-051-0/+1
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* pl011: Move registers' definition in a separate fileJulien Grall2013-08-051-0/+80
| | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org>
* xen: arm: handle traps of conditional instructions.Ian Campbell2013-08-021-0/+9
| | | | | | | | | | | | | This means handling the HSR.ccvalid field as well as correctly processing the Thumb If-Then state block in the CPSR correctly which is rather tricky. KVM provided a useful reference for all this. I suspect we aren't actually hitting these paths very often since the sorts of traps we take will not often be conditional so my limited testing may not actually be exercising these paths very much. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Julien Grall <julien.linaro.org>
* xen/arm: Fix guest secondaries CPU boot after bcac10fJulien Grall2013-07-301-1/+5
| | | | | | | | | | | The commit bcac10f "xen: arm: support building a 64-bit dom0 domain" breaks secondary cpus boot for all the guest. Linux requires CPUs to boot on SVC mode. Divide PSR_GUEST_INIT in 2 distinct defines: one for 32 bit, the other for 64 bits guests. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
* xen: arm: Handle SMC from 64-bit guestsIan Campbell2013-07-291-1/+13
| | | | | | | | Similarly to arm32 guests handle it by injecting an undefined instruction trap. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
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