diff options
| author | Julien Grall <julien.grall@linaro.org> | 2013-08-08 13:56:51 +0100 |
|---|---|---|
| committer | Ian Campbell <ian.campbell@citrix.com> | 2013-08-20 15:17:17 +0100 |
| commit | 2960e5e2aabedb9a188fe7c0483c3df43875abf3 (patch) | |
| tree | 9466844b79c7b5044d5da67bbaec38e2e15894af /xen/include/asm-arm | |
| parent | e1b87f4e531e9ec257bc332859770f3c00b1fbca (diff) | |
| download | xen-2960e5e2aabedb9a188fe7c0483c3df43875abf3.tar.gz xen-2960e5e2aabedb9a188fe7c0483c3df43875abf3.tar.bz2 xen-2960e5e2aabedb9a188fe7c0483c3df43875abf3.zip | |
xen/arm: erratum 766422: decode thumb store during data abort
From the errata document:
When a non-secure non-hypervisor memory operation instruction generates a
stage2 page table translation fault, a trap to the hypervisor will be triggered.
For an architecturally defined subset of instructions, the Hypervisor Syndrome
Register (HSR) will have the Instruction Syndrome Valid (ISV) bit set to 1’b1,
and the Rt field should reflect the source register (for stores) or destination
register for loads.
On Cortex-A15, for Thumb and ThumbEE stores, the Rt value may be incorrect
and should not be used, even if the ISV bit is set. All loads, and all ARM
instruction set loads and stores, will have the correct Rt value if the ISV
bit is set.
To avoid this issue, Xen needs to decode thumb store instruction and update
the transfer register.
Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Diffstat (limited to 'xen/include/asm-arm')
| -rw-r--r-- | xen/include/asm-arm/arm32/processor.h | 4 | ||||
| -rw-r--r-- | xen/include/asm-arm/arm64/processor.h | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index b26625291d..d1b89d0e06 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -111,6 +111,10 @@ struct cpu_user_regs #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) +/* Erratum 766422: only Cortex A15 r0p4 is affected */ +#define cpu_has_erratum_766422() \ + (unlikely(current_cpu_data.midr.bits == 0x410fc0f4)) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index c8d460914e..5bf086711c 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -104,6 +104,8 @@ struct cpu_user_regs #define READ_SYSREG(name) READ_SYSREG64(name) #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) +#define cpu_has_erratum_766422() 0 + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */ |