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author | fishsoupisgood <github@madingley.org> | 2018-05-17 09:39:06 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2018-05-17 09:39:06 +0100 |
commit | aac3a573c21dd7822dad9259757b1cd3f3163054 (patch) | |
tree | c8b585443040dc09da2dd0dd66a7db649f5b5cdf /spdif.vhd | |
parent | 0780df86a9ec88bf8810f7fef1d241030dc1b655 (diff) | |
download | rob_spdif-aac3a573c21dd7822dad9259757b1cd3f3163054.tar.gz rob_spdif-aac3a573c21dd7822dad9259757b1cd3f3163054.tar.bz2 rob_spdif-aac3a573c21dd7822dad9259757b1cd3f3163054.zip |
add silence detection
Diffstat (limited to 'spdif.vhd')
-rw-r--r-- | spdif.vhd | 58 |
1 files changed, 39 insertions, 19 deletions
@@ -52,17 +52,17 @@ architecture rtl of spdif is locked : out std_logic ); end component; + component counter is port ( - divisor : in std_logic_vector (15 downto 0); + divisor : in integer; clk : in std_logic; n_reset : in std_logic; clk_out : out std_logic ); end component; - component spdif_decoder is port ( @@ -80,6 +80,20 @@ architecture rtl of spdif is ); end component; + + component silence_detector is + port + ( + max_ticks : in integer; + clk : in std_logic; + d : in std_logic_vector(23 downto 0); + n_reset : in std_logic; + silent : out std_logic + ); + end component; + + + signal n_reset : std_logic; signal clk_200mhz : @@ -90,9 +104,12 @@ architecture rtl of spdif is std_logic; signal clk1 : std_logic; - signal d1 : std_logic_vector(26 downto 0); - signal bna1 : std_logic; - signal sof1 : std_logic; + signal d1 : std_logic_vector(26 downto 0); + signal bna1 : std_logic; + signal sof1 : std_logic; + signal ready1 : std_logic; + + signal mute1 : std_logic; begin n_reset <= n_rst_in; @@ -105,17 +122,10 @@ begin c0 => clk_200mhz ); --- pll2 : --- pll200 port map ( --- areset => not n_reset, --- inclk0 => xtal_50mhz, --- c0 => clk_100mhz --- ); - div1 : counter port map ( n_reset => n_reset, clk => clk_200mhz, - divisor => x"000c", + divisor => 6, clk_out => clk1 ); @@ -137,21 +147,31 @@ begin bmc_d => dbg6, bna => bna1, d => d1, - ready => dbg7 + ready => ready1 ); + dbg8 <= bna1; + sd1 : silence_detector port map( + n_reset => n_reset, + clk => clk1, + d => d1(26 downto 3), + max_ticks => 33333333, -- 1 second + silent => mute1 + ); + + n_mute_out <= not mute1; + n_stby_out <= '0'; dbg1 <= spdif_clkd1; dbg2 <= clk1; + dbg7 <= ready1; + n_leds(0) <= d1(26); + n_leds(1) <= d1(25); + n_leds(2) <= not mute1; - n_leds(0) <= d1(9); - n_leds(1) <= d1(10); - n_leds(2) <= d1(11); - n_mute_out <= '0'; - n_stby_out <= '0'; end rtl; |