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author | fishsoupisgood <github@madingley.org> | 2018-05-17 09:39:06 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2018-05-17 09:39:06 +0100 |
commit | aac3a573c21dd7822dad9259757b1cd3f3163054 (patch) | |
tree | c8b585443040dc09da2dd0dd66a7db649f5b5cdf /clock_recovery.vhd | |
parent | 0780df86a9ec88bf8810f7fef1d241030dc1b655 (diff) | |
download | rob_spdif-aac3a573c21dd7822dad9259757b1cd3f3163054.tar.gz rob_spdif-aac3a573c21dd7822dad9259757b1cd3f3163054.tar.bz2 rob_spdif-aac3a573c21dd7822dad9259757b1cd3f3163054.zip |
add silence detection
Diffstat (limited to 'clock_recovery.vhd')
-rw-r--r-- | clock_recovery.vhd | 82 |
1 files changed, 0 insertions, 82 deletions
diff --git a/clock_recovery.vhd b/clock_recovery.vhd deleted file mode 100644 index 91de224..0000000 --- a/clock_recovery.vhd +++ /dev/null @@ -1,82 +0,0 @@ - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.numeric_std.all; - -entity clock_recovery is - port - ( - n_reset : in std_logic; - - clk : in std_logic; - d_in : in std_logic; - clk_out : out std_logic - ); -end clock_recovery; - -architecture rtl of clock_recovery is - - - signal qish : - std_logic; - signal od : - std_logic; - signal edge : - std_logic; - signal period : - std_logic_vector(15 downto 0); - signal divisor : - std_logic_vector(15 downto 0); - signal counter : - std_logic_vector(15 downto 0); -begin - - - process(clk, d_in, od, n_reset) - begin - if n_reset = '0' then - od <= '0'; - elsif RISING_EDGE(clk) then - od <= d_in; - end if; - end process; - - edge <= d_in xor od; - divisor <= x"0007"; - - process(edge, n_reset, clk, divisor, counter, qish, period) - begin - if n_reset = '0' then - period <= (others => '0'); - counter <= (others => '0'); - qish <= '0'; - elsif RISING_EDGE(clk) then - if edge = '0' then - period <= period +1; - - if counter < divisor then - counter <= counter + 1; - else - counter <= (others => '0'); - qish <= not qish; - end if; - else - period <= (others => '0'); - counter <= (others => '0'); - qish <= '0'; --- if period<divisor then --- divisor <= divisor -1; --- else --- divisor <= divisor + 1; --- end if; - - end if; - end if; - end process; - - clk_out <= qish; - -end rtl; - |