Just one freq supported

3 files changed, 31 insertions, 28 deletions

diff --git a/spdif.qsf b/spdif.qsf
index 31333b7..1cb54fa 100644
--- a/spdif.qsf
+++ b/spdif.qsf
@@ -52,8 +52,9 @@ set_global_assignment -name FAMILY "Cyclone II"
     set_location_assignment PIN_118 -to dbg[6]
     set_location_assignment PIN_119 -to dbg[7]
     set_global_assignment -name USE_CONFIGURATION_DEVICE on
-    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
     set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
 
     set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
     set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/spdif.sdc b/spdif.sdc
index e0eb00c..f7c36c5 100644
--- a/spdif.sdc
+++ b/spdif.sdc
@@ -7,9 +7,9 @@ set_time_format -unit ns -decimal_places 3
 ##############################################################################
 # Create Input reference clocks
 create_clock -name {xtal_50mhz} -period 20.000 -waveform { 0.000 10.000 } [get_ports { xtal_50mhz }]
-create_clock -name {det1_clk} -period 10.000 -waveform { 0.000 5.000 } [get_nets { det1|divider:div1|q }]
+# create_clock -name {det1_clk} -period 10.000 -waveform { 0.000 5.000 } [get_nets { det1|divider:div1|q }]
 create_clock -name {det2_clk} -period 25.000 -waveform { 0.000 12.500 } [get_nets { det2|divider:div1|q }]
-create_clock -name {det3_clk} -period 40.000 -waveform { 0.000 20.000 } [get_nets { det3|divider:div1|q }]
+# create_clock -name {det3_clk} -period 40.000 -waveform { 0.000 20.000 } [get_nets { det3|divider:div1|q }]
 
 ##############################################################################
 # Now that we have created the custom clocks which will be base clocks,
diff --git a/spdif.vhd b/spdif.vhd
index 0339bad..ce2f584 100644
--- a/spdif.vhd
+++ b/spdif.vhd
@@ -75,18 +75,18 @@ begin
             );
 
     -- 96000Hz
-    det1 : detector port map (
-        n_reset  => n_reset,
-        clk_in   => clk_200mhz,
-        spdif_in => spdif_in,
-
-        divisor       => 2,  -- divisor to turn clk_in into 6x spdif base frequency
-        silent_thresh => 96000,  -- number of samples of same sample before we declare silence
-        valid_divisor => 100000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
-        valid_thresh  => 90000,  -- number of valid samples that must be received in validity period to declare it's all ok.
-
-        mute => mute1
-        );
+--    det1 : detector port map (
+--        n_reset  => n_reset,
+--        clk_in   => clk_200mhz,
+--        spdif_in => spdif_in,
+--
+--        divisor       => 2,  -- divisor to turn clk_in into 6x spdif base frequency
+--        silent_thresh => 96000,  -- number of samples of same sample before we declare silence
+--        valid_divisor => 100000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
+--        valid_thresh  => 90000,  -- number of valid samples that must be received in validity period to declare it's all ok.
+--
+--        mute => mute1
+--        );
 
 
     -- 44100Hz
@@ -105,19 +105,21 @@ begin
         );
 
     -- 32000Hz
-    det3 : detector port map (
-        n_reset  => n_reset,
-        clk_in   => clk_200mhz,
-        spdif_in => spdif_in,
-
-        divisor       => 8,  -- divisor to turn clk_in into 6x spdif base frequency
-        silent_thresh => 32000,  -- number of samples of same sample before we declare silence
-        valid_divisor => 25000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
-        valid_thresh  => 30000,  -- number of valid samples that must be received in validity period to declare it's all ok.
-
-        mute => mute3
-        );
-
+--    det3 : detector port map (
+--        n_reset  => n_reset,
+--        clk_in   => clk_200mhz,
+--        spdif_in => spdif_in,
+--
+--        divisor       => 8,  -- divisor to turn clk_in into 6x spdif base frequency
+--        silent_thresh => 32000,  -- number of samples of same sample before we declare silence
+--        valid_divisor => 25000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
+--        valid_thresh  => 30000,  -- number of valid samples that must be received in validity period to declare it's all ok.
+--
+--        mute => mute3
+--        );
+
+	 mute1 <= '1';
+	 mute3 <= '1';
     mute <= mute1 and mute2 and mute3;
 
     n_mute_out <= not mute;