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-rw-r--r--cpld/Makefile74
-rw-r--r--cpld/laser.qpf30
-rw-r--r--cpld/laser.qsf129
-rw-r--r--cpld/laser.sdc0
-rw-r--r--cpld/laser.vhd213
-rwxr-xr-xcpld/tools/wrap15
6 files changed, 461 insertions, 0 deletions
diff --git a/cpld/Makefile b/cpld/Makefile
new file mode 100644
index 0000000..d951aa3
--- /dev/null
+++ b/cpld/Makefile
@@ -0,0 +1,74 @@
+PROJ=laser
+
+SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
+
+SOF=${PROJ}.sof
+POF=${PROJ}.pof
+JIC=${PROJ}.jic
+
+default: flash.stamp
+
+
+
+sta.stamp:asm.stamp
+ tools/wrap quartus_sta ${PROJ} -c ${PROJ}
+ touch $@
+
+asm.stamp:fit.stamp
+ tools/wrap quartus_asm --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
+ touch $@
+
+${POF} ${SOF}:asm.stamp
+
+fit.stamp: ans.stamp
+ tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
+ touch $@
+
+ans.stamp: ${SRCS}
+ tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ}
+ touch $@
+
+sim.stamp: fit.stamp
+ tools/wrap quartus_eda ${PROJ} --simulation --tool=modelsim --format=verilog
+
+
+#${JIC}:${SOF}
+# tools/wrap quartus_cpf -c ${PROJ}.cof
+
+
+#load_sof.stamp: ${SOF}
+# tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
+
+
+#flash:${JIC}
+# tools/wrap quartus_pgm -m JTAG -o "ip;${JIC}"
+# tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
+
+
+flash: flash.stamp
+flash.stamp: ${POF}
+ tools/wrap quartus_pgm -m JTAG -o "p;${POF}"
+ touch $@
+
+
+
+
+sim netlist: sim.stamp
+
+quartus:
+ tools/wrap quartus ${PROJ}.qpf
+
+jtagd:
+ sudo killall jtagd || true
+ sudo tools/wrap jtagd
+
+clean:
+ /bin/rm -rf ${BSP_DIR} db incremental_db src/obj simulation
+ /bin/rm -f ${SOPC_FILE} src/Makefile elf.flash sof.flash *.stamp ${SOF} ${ELF} *.rpt *.html *.summary *.pin *.jdi *.qws *.pof *.smsg *.map *.jic
+ /bin/rm -f src/${PROJ}.objdump src/${PROJ}.map
+ /bin/rm -f sopc_builder_log.txt src/*~ SDIF/*~
+ /bin/rm -f sim.stamp
+
+
+
+
diff --git a/cpld/laser.qpf b/cpld/laser.qpf
new file mode 100644
index 0000000..7b035fc
--- /dev/null
+++ b/cpld/laser.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Web Edition
+# Date created = 21:48:38 September 12, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.0"
+DATE = "21:48:38 September 12, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "laser"
diff --git a/cpld/laser.qsf b/cpld/laser.qsf
new file mode 100644
index 0000000..151e94e
--- /dev/null
+++ b/cpld/laser.qsf
@@ -0,0 +1,129 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Web Edition
+# Date created = 21:48:38 September 12, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# laser.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY laser
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:48:38 SEPTEMBER 12, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+
+
+# board assignments
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_por
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to laser
+
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to dbg[7]
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS ON
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+#set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 1
+
+set_global_assignment -name POWER_USE_TA_VALUE 35
+
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+#yellow (2.83Mhz)
+set_location_assignment PIN_12 -to iis_sclk
+
+#orange (11Mhz)
+set_location_assignment PIN_15 -to iis_mclk
+
+#red
+set_location_assignment PIN_17 -to iis_sdin
+
+#brown (44.1kHz)
+set_location_assignment PIN_19 -to iis_lrclk
+
+set_location_assignment PIN_27 -to laser_out
+
+set_location_assignment PIN_37 -to diff0_minus
+set_location_assignment PIN_39 -to diff0_plus
+
+set_location_assignment PIN_44 -to n_por
+
+
+set_location_assignment PIN_62 -to test_clk;
+
+set_location_assignment PIN_64 -to clk_50mhz
+
+
+set_location_assignment PIN_74 -to dbg[0]
+set_location_assignment PIN_76 -to dbg[1]
+set_location_assignment PIN_78 -to dbg[2]
+set_location_assignment PIN_82 -to dbg[3]
+set_location_assignment PIN_84 -to dbg[4]
+set_location_assignment PIN_86 -to dbg[5]
+set_location_assignment PIN_88 -to dbg[6]
+set_location_assignment PIN_90 -to dbg[7]
+
+#set_location_assignment PIN_88 -to diff1_plus
+#set_location_assignment PIN_90 -to diff1_minus
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SOURCE_FILE laser.cof
+set_global_assignment -name PIN_FILE laser.pin
+set_global_assignment -name VHDL_FILE laser.vhd
+
diff --git a/cpld/laser.sdc b/cpld/laser.sdc
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/cpld/laser.sdc
diff --git a/cpld/laser.vhd b/cpld/laser.vhd
new file mode 100644
index 0000000..cfa1c87
--- /dev/null
+++ b/cpld/laser.vhd
@@ -0,0 +1,213 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity laser is
+ port (
+ n_por : in std_logic;
+ clk_50mhz : in std_logic;
+
+ iis_sdin : in std_logic;
+ iis_sclk : in std_logic;
+ iis_lrclk : in std_logic;
+ iis_mclk : in std_logic;
+
+
+ laser_out : out std_logic;
+
+ dbg : out std_logic_vector(7 downto 0)
+ );
+end laser;
+
+architecture rtl of laser is
+
+ signal sdin_sr:
+ std_logic_vector(32 downto 0);
+ signal lrclk_sr:
+ std_logic_vector(32 downto 0);
+ signal l:
+ std_logic_vector(15 downto 0);
+ signal r:
+ std_logic_vector(15 downto 0);
+ signal sample_clock:
+ std_logic;
+
+ signal last_lrclk :
+ std_logic;
+ signal sample_clk :
+ std_logic;
+
+ signal laser:
+ std_logic;
+
+ signal laser_sr:
+ std_logic_vector(31 downto 0);
+
+ signal sr:
+ std_logic_vector(3 downto 0);
+ signal sl:
+ std_logic_vector(3 downto 0);
+
+ signal se:
+ std_logic;
+
+ signal safety:
+ std_logic;
+
+ signal safety_counter:
+ std_logic_vector(31 downto 0);
+
+
+ signal n_reset: std_logic;
+
+-- signal ticks:
+-- std_logic_vector(31 downto 0);
+-- signal toggle: std_logic;
+
+begin
+
+ dbg(0) <= iis_sdin;
+ dbg(1) <= iis_sclk;
+ dbg(2) <= iis_lrclk;
+ dbg(3) <= iis_mclk;
+
+ dbg(4) <= se;
+ dbg(5) <= '0';
+ dbg(6) <= '0';
+ dbg(7) <= '0';
+
+ n_reset <= n_por;
+
+
+
+ -- iis shift register, latch bits on rising edge of sample_clk
+ -- detect edges in lrclk and copy to l and r registers on falling edge
+ -- generate a sample clock whose rising edge is 1 sclk after data is latched
+ -- and therefor 1.5sclk after data arrives
+
+ process(iis_sclk,iis_sdin,iis_lrclk,sdin_sr,lrclk_sr,n_reset)
+ begin
+
+ if n_reset ='0' then
+ sdin_sr <= (others => '0');
+ lrclk_sr <= (others => '0');
+ sample_clk <='1';
+ l<=(others => '0');
+ r<=(others => '0');
+ else
+
+ if rising_edge(iis_sclk) then
+ sdin_sr <= sdin_sr(31 downto 0) & iis_sdin;
+ lrclk_sr <= lrclk_sr(31 downto 0) & iis_lrclk;
+ end if;
+
+ if falling_edge(iis_sclk) then
+ -- new data for left channel
+ if (lrclk_sr(1) = '0') and (lrclk_sr(0) ='1') then
+ l <=sdin_sr(31 downto 16);
+ end if;
+
+ -- new data for right channel
+ if (lrclk_sr(1) = '1') and (lrclk_sr(0) ='0') then
+ r <=sdin_sr(31 downto 16);
+ sample_clk <='0';
+ else
+ sample_clk <='1';
+ end if;
+ end if;
+ end if;
+
+ end process;
+
+
+ -- drive the laser from the xor of the LSBs
+ laser <= not(l(0) xor r(0));
+
+ -- make sample clock based shift register of
+ -- laser because DAC has latency
+ process(sample_clk,laser,laser_sr,n_reset)
+ begin
+ if n_reset ='0' then
+ laser_sr <= (others => '0');
+ elsif rising_edge(sample_clk) then
+ laser_sr <= laser_sr(30 downto 0) & laser;
+ end if;
+ end process;
+
+
+ -- safety system
+ -- see if there are changes in a bit of either the
+ -- left or right channels in 0.5s
+ -- run this from a different clock domain incase sample_clk stops
+
+ -- resample the l and r bits into new clock domain
+ -- with shift register
+
+ process(clk_50mhz,sl,sr,l,r,safety_counter,n_reset)
+ begin
+ if n_reset ='0' then
+ sl <= (others => '0');
+ sr <= (others => '0');
+ elsif rising_edge(clk_50mhz) then
+ sl <= sl(2 downto 0) & l(12);
+ sr <= sr(2 downto 0) & r(12);
+ end if;
+ end process;
+
+ -- detect changes in either bit
+ se<=(sl(3) xor sl(2)) or (sr(3) xor sr(2));
+
+ process(clk_50mhz,se,safety_counter,n_reset)
+ begin
+ -- count how long since a bit changed
+ if n_reset ='0' then
+ safety_counter <= (others => '0');
+ elsif falling_edge(clk_50mhz) then
+ if se='1' then
+ safety_counter <= (others => '0');
+ else
+ safety_counter <= safety_counter + 1;
+ end if;
+ end if;
+
+ -- if it's too long blank the beam
+ if n_reset ='0' then
+ safety <= '0';
+ elsif rising_edge(clk_50mhz) then
+ if (safety_counter>1000000) then
+ safety <= '0';
+ else
+ safety <= '1';
+ end if;
+ end if;
+ end process;
+
+
+ laser_out <= laser_sr(10) and safety;
+-- laser_out <= laser;
+
+
+-- process(test_clk,ticks,n_reset)
+-- begin
+-- if n_reset ='0' then
+-- ticks <= (others => '0');
+-- toggle <= '0';
+-- elsif rising_edge(test_clk) then
+-- if ticks < (22050 * 32) then
+-- ticks <= ticks + 1;
+-- else
+-- toggle <= not toggle;
+-- ticks <= (others => '0');
+-- end if;
+-- end if;
+-- end process;
+--
+--
+-- laser_out <= toggle;
+
+
+end rtl;
+
diff --git a/cpld/tools/wrap b/cpld/tools/wrap
new file mode 100755
index 0000000..26a0640
--- /dev/null
+++ b/cpld/tools/wrap
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+AD=/software/apps/altera/quartus_ii_13.0sp1
+if [ $(uname -m ) == "x86_64" ]; then
+ LL=linux64
+else
+ LL=linux
+fi
+QUARTUS_ROOTDIR="${AD}/quartus"
+PATH="${AD}/quartus/bin:${AD}/quartus/sopc_builder/bin:${AD}/nios2eds/sdk2/bin:${AD}/nios2eds/bin:${AD}/nios2eds/bin/gnu/H-i686-pc-linux-gnu/bin:${PATH}"
+LD_LIBRARY_PATH="${AD}/quartus/${LL}:${LD_LIBRARY_PATH}"
+
+export LD_LIBRARY_PATH PATH QUARTUS_ROOTDIR
+
+"$@"
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