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* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* sv: carry over global typedefs from previous filesZachary Snow2021-03-172-0/+60
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-0/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* blackbox: Include whiteboxed modulesgatecat2021-03-171-0/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-0/+29
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* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-151-0/+31
| | | | | | | | | | | | | | | | | The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-151-11/+20
| | | | Fixes #2546.
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-151-0/+14
| | | | | | | | | Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+20
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+16
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-082-2/+1
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* proc_dff: Fix emitted FF when a register is not assigned in async resetMarcelina Kościelnicka2021-03-081-0/+23
| | | | Fixes #2619.
* tests/bram: Do not generate write address collisions.Marcelina Kościelnicka2021-03-081-5/+23
| | | | These have no defined semantics, making the tests non-deterministic.
* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-0710-0/+177
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-0210-0/+177
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-072-0/+33
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-042-0/+33
| |/ | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* / sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-062-0/+47
|/ | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-012-0/+61
| | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-017-0/+159
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Set aside extraneous tests in simple_abc9 test suiteZachary Snow2021-03-012-0/+19
| | | | | | | New test cases on one branch may be automatically copied from simple/ to simple_abc9/, causing failures when switching to another branch. This updates the simple_abc9 script to set aside extraneous tests in a non-destructive way.
* Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-016-0/+56
|\ | | | | genrtlil: improve name conflict error messaging
| * genrtlil: improve name conflict error messagingZachary Snow2021-02-266-0/+56
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* | sv: extended support for integer typesZachary Snow2021-02-284-0/+78
| | | | | | | | | | | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* | Add tests for $countbitsMichael Singer2021-02-262-0/+76
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* Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-242-0/+438
| | | | turn-off (#2566)
* Add tests for some common techmap files.Marcelina Kościelnicka2021-02-243-0/+50
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* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-238-37/+94
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-218-37/+94
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ↵William D. Jones2021-02-231-1/+1
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* | machxo2: Update tribuf test to reflect active-low OE.William D. Jones2021-02-231-1/+2
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* | machxo2: Add believed-to-be-correct tribuf test.William D. Jones2021-02-231-0/+9
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* | machxo2: Add passing fsm, mux, and shifter tests.William D. Jones2021-02-233-0/+65
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* | machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.William D. Jones2021-02-233-3/+11
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* | machxo2: Add dffe test.William D. Jones2021-02-231-0/+9
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* | machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-231-0/+10
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* | machxo2: Add test/arch/machxo2 directory (test does not pass).William D. Jones2021-02-233-0/+14
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* | assertpmux: Fix crash on unused $pmux output.Marcelina Kościelnicka2021-02-221-0/+18
| | | | | | | | Fixes #2595.
* | Merge pull request #2586 from zachjs/tern-recursewhitequark2021-02-212-0/+76
|\ \ | | | | | | verilog: support recursive functions using ternary expressions
| * | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-122-0/+76
| |/ | | | | | | | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* / verilog: error on macro invocations with missing argument listsZachary Snow2021-02-192-0/+22
|/ | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-0/+94
|\ | | | | verilog: refactored constant function evaluation
| * verilog: refactored constant function evaluationZachary Snow2021-02-042-0/+94
| | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-112-0/+22
|\ \ | | | | | | verlog: allow shadowing module ports within generate blocks
| * | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-072-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-0/+19
|/ / | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-052-7/+28
| | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+26
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0423-6/+495
|\ | | | | verilog: significant block scoping improvements
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