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| * update testPepijn de Vos2019-12-031-2/+3
| * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-10/+12
| * attempt to fix formattingPepijn de Vos2019-11-251-138/+138
| * gowin: add and test dff init valuesPepijn de Vos2019-11-252-0/+296
* | abc9: Fix breaking of SCCsDavid Shah2019-12-011-0/+6
* | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-271-0/+69
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| * | No need for -abc9Eddie Hung2019-11-261-1/+1
| * | Add citationEddie Hung2019-11-261-0/+1
| * | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
* | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fixClifford Wolf2019-11-271-0/+13
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| * | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-271-0/+13
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* / / Remove notesEddie Hung2019-11-261-9/+0
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* | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-5/+16
* | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-254-8/+8
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* Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-221-0/+63
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| * sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
* | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
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* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1912-0/+248
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| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-165-17/+34
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-0/+11
| * | fix wide lutsPepijn de Vos2019-11-061-7/+10
| * | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
| * | add tristate buffer and testPepijn de Vos2019-10-281-0/+13
| * | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
| * | ALU sim tweaksPepijn de Vos2019-10-241-2/+2
| * | Add some testsPepijn de Vos2019-10-2110-0/+224
* | | Fix #1462, #1480.Marcin Kościelnicki2019-11-192-0/+29
* | | Fix #1496.Marcin Kościelnicki2019-11-181-0/+13
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* | Fixed testsMiodrag Milanovic2019-11-115-17/+34
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* fixed errorMiodrag Milanovic2019-10-181-1/+1
* Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
* Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
* Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
* Share common testsMiodrag Milanovic2019-10-18103-1316/+178
* fix yosys pathMiodrag Milanovic2019-10-181-2/+2
* Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18150-0/+0
* Add async2syncMiodrag Milanovic2019-10-182-8/+8
* Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1893-59/+1832
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| * Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-1873-59/+1403
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| | * Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-1843-59/+763
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| | | * hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
| | | * Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
| | | * remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
| | | * remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
| | | * split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
| | | * Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
| | | * Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
| | | * Fix formattingMiodrag Milanovic2019-10-171-1/+8
| | | * Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
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