| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1046 from bogdanvuk/master | Clifford Wolf | 2019-06-28 | 2 | -0/+17 |
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| | * | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-27 | 12 | -5/+878 |
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| | * | | Refactor "opt_rmdff -sat" | Clifford Wolf | 2019-06-20 | 2 | -14/+12 |
| | * | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext... | Clifford Wolf | 2019-06-20 | 2 | -0/+19 |
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| | | * \ | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-14 | 43 | -32/+447 |
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| | | * | | | Optimizing DFFs whose initial value prevents their value from changing | Bogdan Vukobratovic | 2019-05-28 | 2 | -0/+19 |
| * | | | | | Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog | Eddie Hung | 2019-06-27 | 1 | -0/+18 |
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| | * | | | | | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 |
| | * | | | | | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 1 | -0/+8 |
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| * | | | | | Merge pull request #1143 from YosysHQ/clifford/fix1135 | Eddie Hung | 2019-06-27 | 2 | -5/+26 |
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| | * | | | | | Add #1135 testcase | Eddie Hung | 2019-06-27 | 2 | -5/+26 |
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| * / / / / | Copy tests from eddie/fix1132 | Eddie Hung | 2019-06-27 | 1 | -0/+320 |
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| * | | | | Add testcase from #335, fixed by #1130 | Eddie Hung | 2019-06-25 | 1 | -0/+28 |
| * | | | | Merge pull request #1130 from YosysHQ/eddie/fix710 | Clifford Wolf | 2019-06-25 | 2 | -1/+22 |
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| | * | | | | Add test | Eddie Hung | 2019-06-24 | 2 | -1/+22 |
| * | | | | | Merge remote-tracking branch 'origin/master' into eddie/muxpack | Eddie Hung | 2019-06-22 | 5 | -1/+298 |
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| | * | | | | Merge pull request #1108 from YosysHQ/clifford/fix1091 | Eddie Hung | 2019-06-21 | 1 | -1/+140 |
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| | | * | | | | Missing a `clean` and `opt_expr -mux_bool` in test | Eddie Hung | 2019-06-20 | 1 | -0/+4 |
| | | * | | | | Add test | Eddie Hung | 2019-06-20 | 1 | -1/+136 |
| | * | | | | | Merge pull request #1085 from YosysHQ/eddie/shregmap_improve | Eddie Hung | 2019-06-21 | 2 | -0/+114 |
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| | | * | | | | | Add shregmap -tech xilinx test | Eddie Hung | 2019-06-12 | 2 | -2/+63 |
| | | * | | | | | Add test | Eddie Hung | 2019-06-10 | 2 | -0/+53 |
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| | * | | | | | Merge pull request #1119 from YosysHQ/eddie/fix1118 | Clifford Wolf | 2019-06-21 | 1 | -0/+11 |
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| | | * | | | | | Add test | Eddie Hung | 2019-06-20 | 1 | -0/+11 |
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| | * | | | | | Extend sign extension tests | Eddie Hung | 2019-06-20 | 1 | -4/+16 |
| | * | | | | | Remove leftover comment | Eddie Hung | 2019-06-20 | 1 | -3/+0 |
| | * | | | | | Add test | Eddie Hung | 2019-06-20 | 1 | -0/+24 |
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| * | | | | | Add more tests | Eddie Hung | 2019-06-21 | 2 | -21/+51 |
| * | | | | | Fix testcase | Eddie Hung | 2019-06-21 | 1 | -3/+4 |
| * | | | | | Add more muxpack tests, with overlapping entries | Eddie Hung | 2019-06-21 | 2 | -1/+84 |
| * | | | | | Merge branch 'master' into eddie/muxpack | Eddie Hung | 2019-06-21 | 6 | -21/+62 |
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| | * | | | | Update some .gitignore files | Clifford Wolf | 2019-06-20 | 2 | -3/+3 |
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| | * | | | Add proper test for SV-style arrays | Clifford Wolf | 2019-06-20 | 3 | -6/+16 |
| | * | | | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo... | Clifford Wolf | 2019-06-20 | 2 | -0/+6 |
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| | | * | | | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 2 | -0/+6 |
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| | * | | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinit | Clifford Wolf | 2019-06-19 | 2 | -14/+37 |
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| | | * | | | Add defvalue test, minor autotest fixes for .sv files | Clifford Wolf | 2019-06-19 | 2 | -14/+37 |
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| | * / / | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 |
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| * | | | Merge remote-tracking branch 'origin/master' into eddie/muxpack | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
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| | * | | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
| * | | | Merge branch 'master' into eddie/muxpack | Eddie Hung | 2019-06-07 | 28 | -33/+138 |
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| | * | | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
| | * | | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 |
| | * | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
| | * | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
| | * | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 2 | -0/+31 |
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| | | * \ | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 2 | -0/+31 |
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| | | | * | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 2 | -0/+31 |
| | * | | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 |
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| | * | | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 2 | -12/+1 |
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index : iCE40/yosys | |
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