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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 12:31:15 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-27 12:31:15 -0700 |
| commit | c4c39e98146b6837c35c425ef7987b2be45c0451 (patch) | |
| tree | 5db6facf6aebcad0777fa1014381ad5233f24733 /tests | |
| parent | eab8384ec7108db62573567f9fbceca62adfdbe5 (diff) | |
| parent | ab7c4319058bbae8758cda9f246c92c324dfafbf (diff) | |
| download | yosys-c4c39e98146b6837c35c425ef7987b2be45c0451.tar.gz yosys-c4c39e98146b6837c35c425ef7987b2be45c0451.tar.bz2 yosys-c4c39e98146b6837c35c425ef7987b2be45c0451.zip | |
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
tests: Check that Icarus can parse arch sim models
Diffstat (limited to 'tests')
| -rwxr-xr-x | tests/arch/run-test.sh | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh new file mode 100755 index 000000000..5292d1615 --- /dev/null +++ b/tests/arch/run-test.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -e + +echo "Running syntax check on arch sim models" +for arch in ../../techlibs/*; do + find $arch -name cells_sim.v | while read path; do + echo -n "Test $path ->" + iverilog -t null -I$arch $path + echo " ok" + done +done + +for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do + echo -n "Test $path ->" + iverilog -t null $path + echo " ok" +done |