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authorEddie Hung <eddie@fpgeh.com>2019-06-27 11:13:49 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-27 11:13:49 -0700
commitab7c4319058bbae8758cda9f246c92c324dfafbf (patch)
treed451e5aedb59ef71a5318627f8f66cefbfcd4f89 /tests
parent71b046d63996a1813375e56f44543e58eb7e1b5e (diff)
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Add simcells.v, simlib.v, and some output
Diffstat (limited to 'tests')
-rwxr-xr-xtests/arch/run-test.sh12
1 files changed, 11 insertions, 1 deletions
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index fc4175be8..5292d1615 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -4,5 +4,15 @@ set -e
echo "Running syntax check on arch sim models"
for arch in ../../techlibs/*; do
- find $arch -name cells_sim.v -print0 | xargs -0 -n1 -r iverilog -t null -I$arch
+ find $arch -name cells_sim.v | while read path; do
+ echo -n "Test $path ->"
+ iverilog -t null -I$arch $path
+ echo " ok"
+ done
+done
+
+for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
+ echo -n "Test $path ->"
+ iverilog -t null $path
+ echo " ok"
done