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* genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-4/+9
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* Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-221-0/+9
|\ | | | | Allow constant function calls in constant function arguments
| * Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+9
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* | Sign extend port connections where necessaryZachary Snow2020-12-182-0/+98
|/ | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Merge pull request #2133 from dh73/nodev_headClaire Xen2020-11-2518-65/+322
|\ | | | | Adding latch tests for shift&mask AST dynamic part-select enhancements
| * Removing trailing whitespacediego2020-06-101-30/+30
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| * Adding latch tests for shift&mask AST dynamic part-select enhancementsdiego2020-06-0918-68/+325
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* | nexus: DSP inference supportDavid Shah2020-11-201-12/+34
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
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* | xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
| | | | | | | | | | | | | | | | | | | | This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.
* | memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+24
| | | | | | | | | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* | Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1915-0/+298
|\ \ | | | | | | synth_nexus: Initial implementation
| * | synth_nexus: Initial implementationDavid Shah2020-10-1515-0/+298
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* | | Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-011-0/+61
|\ \ \ | | | | | | | | Added $high(), $low(), $left(), $right()
| * | | We can now handle array slices (e.g. $size(x[1]) etc. )Udi Finkelstein2020-09-171-2/+14
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| * | | Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-0/+49
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* | | | Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-0121-230/+156
|\ \ \ \ | | | | | | | | | | Clean up and parallelize testsuite
| * | | | tests: add gitignores for auto-generated makefilesXiretza2020-09-262-0/+2
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| * | | | tests/simple: remove "nullglob" shoptXiretza2020-09-211-1/+0
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| * | | | tests: ParallelizeXiretza2020-09-213-9/+20
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| * | | | tests: Centralize test collection and Makefile generationXiretza2020-09-2116-222/+136
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* | | | | Update .gitignoreDavid Shah2020-10-011-0/+2
| |_|/ / |/| | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | add testsN. Engelhardt2020-09-282-0/+49
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* | | | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* | | | switch argument order to work with macOS getoptN. Engelhardt2020-09-231-1/+1
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* | | Merge pull request #2329 from antmicro/arrays-fix-multirange-sizeclairexen2020-09-171-0/+16
|\ \ \ | | | | | | | | Rewrite multirange arrays sizes [n] as [n-1:0]
| * | | Test multirange (unpacked) arrays sizeLukasz Dalek2020-08-031-0/+16
| | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | | | Merge pull request #2330 from antmicro/arrays-fix-multirange-accessclairexen2020-09-171-0/+12
|\ \ \ \ | |_|/ / |/| | | Fix unsupported subarray access detection
| * | | Add test for subarray access on multidimensional arraysLukasz Dalek2020-08-031-0/+12
| |/ / | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | | Merge pull request #2369 from Xiretza/gitignoresMiodrag Milanović2020-09-101-2/+2
|\ \ \ | | | | | | | | Add missing gitignores for test artifacts
| * | | Add missing gitignores for test artifactsXiretza2020-08-311-2/+2
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* | | | Merge pull request #2352 from zachjs/const-func-localparamclairexen2020-09-011-3/+6
|\ \ \ \ | | | | | | | | | | Allow localparams in constant functions
| * | | | Allow localparams in constant functionsZachary Snow2020-08-201-3/+6
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* | | | | Merge pull request #2353 from zachjs/top-scopeclairexen2020-09-011-0/+16
|\ \ \ \ \ | | | | | | | | | | | | Module name scope support
| * | | | | Module name scope supportZachary Snow2020-08-201-0/+16
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* | | | | Merge pull request #2365 from zachjs/const-arg-loop-split-typeclairexen2020-09-011-0/+20
|\ \ \ \ \ | |_|/ / / |/| | | | Fix constant args used with function ports split across declarations
| * | | | Fix constant args used with function ports split across declarationsZachary Snow2020-08-291-0/+20
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* | | | Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-271-0/+11
|\ \ \ \ | | | | | | | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-261-0/+11
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* / / / intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-262-6/+44
|/ / / | | | | | | | | | | | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* | | Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixesclairexen2020-08-202-14/+3
|\ \ \ | | | | | | | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.
| * | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-202-14/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* | | | Merge pull request #2344 from YosysHQ/mwk/opt_share-fixesclairexen2020-08-203-0/+54
|\ \ \ \ | | | | | | | | | | opt_share: Refactor, fix some bugs.
| * | | | opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-173-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* | | | | Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signedclairexen2020-08-201-0/+11
|\ \ \ \ \ | | | | | | | | | | | | peeopt.shiftmul: Add a signedness check.
| * | | | | peeopt.shiftmul: Add a signedness check.Marcelina Kościelnicka2020-08-051-0/+11
| | |_|/ / | |/| | | | | | | | | | | | | Fixes #2332.
* | | | | Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-203-193/+129
|\ \ \ \ \ | | | | | | | | | | | | Remove passes redundant with opt_dff
| * | | | | Remove now-redundant dff2dffs pass.Marcelina Kościelnicka2020-08-071-50/+0
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| * | | | | peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-072-143/+129
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