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| author | clairexen <claire@symbioticeda.com> | 2020-08-20 16:25:56 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-20 16:25:56 +0200 |
| commit | d9dd8bc74803789835533b81c35c927a80f6c28f (patch) | |
| tree | 9c37e25f0c73d9465a0e09f33215ff3b8418ac68 /tests | |
| parent | a96df40814244830cd0f2b5404507fadb23b2d9a (diff) | |
| parent | 50d532f01c3703930240e30c72b726fa66095cf5 (diff) | |
| download | yosys-d9dd8bc74803789835533b81c35c927a80f6c28f.tar.gz yosys-d9dd8bc74803789835533b81c35c927a80f6c28f.tar.bz2 yosys-d9dd8bc74803789835533b81c35c927a80f6c28f.zip | |
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/intel_alm/mux.ys | 5 | ||||
| -rw-r--r-- | tests/techmap/shiftx2mux.ys | 12 |
2 files changed, 3 insertions, 14 deletions
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index 01cc78e1b..ac3b9b08f 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -70,8 +70,9 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 5 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D +select -assert-max 2 t:MISTRAL_ALUT5 +select -assert-max 5 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys index eb29680f6..f749e79b2 100644 --- a/tests/techmap/shiftx2mux.ys +++ b/tests/techmap/shiftx2mux.ys @@ -74,12 +74,6 @@ design -save gold design -load gold -techmap -D NO_LSB_FIRST_SHIFT_SHIFTX -abc -lut 6 -select -assert-min 17 t:$lut - - -design -load gold techmap abc -lut 6 select -assert-count 16 t:$lut @@ -92,12 +86,6 @@ sat -verify -prove-asserts -show-ports miter design -load gold -techmap -D NO_LSB_FIRST_SHIFT_SHIFTX -abc9 -lut 6 -select -assert-min 17 t:$lut - - -design -load gold techmap abc9 -lut 6 select -assert-count 16 t:$lut |