| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 1 | -0/+46 | |
| |\ \ \ | | | | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset | |||||
| | * | | | Bugfix in partsel.v signed indices test cases | Claire Wolf | 2020-05-02 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| | * | | | Add tests based on the test case from #1990 | Claire Wolf | 2020-05-02 | 1 | -0/+46 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| * | | | | Merge pull request #2028 from zachjs/master | Eddie Hung | 2020-05-06 | 2 | -0/+17 | |
| |\ \ \ \ | | | | | | | | | | | verilog: allow null gen-if then block | |||||
| | * | | | | verilog: allow null gen-if then block | Zachary Snow | 2020-05-06 | 2 | -0/+17 | |
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| * | | | | Merge pull request #2024 from YosysHQ/eddie/primitive_src | Eddie Hung | 2020-05-05 | 1 | -0/+16 | |
| |\ \ \ \ | | | | | | | | | | | verilog: set src attribute for primitives | |||||
| | * | | | | tests: add tests for primitives' src | Eddie Hung | 2020-05-04 | 1 | -0/+16 | |
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| * / / / | verilog: fix specify src attribute | Eddie Hung | 2020-05-04 | 1 | -0/+6 | |
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| * | | | Merge pull request #2014 from YosysHQ/claire/fixoptalu | Claire Wolf | 2020-05-03 | 1 | -0/+12 | |
| |\ \ \ | | | | | | | | | Fix the other "opt_expr -fine" bug introduced in 213a89558 | |||||
| | * | | | test: add test for #2014 | Eddie Hung | 2020-05-02 | 1 | -0/+12 | |
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| * / / | tests: aiger test for wire->start_offset != 0 | Eddie Hung | 2020-05-02 | 2 | -0/+41 | |
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| * / | Add testcase for #2010 | Eddie Hung | 2020-05-01 | 1 | -0/+10 | |
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| * | intel_alm: work around a Quartus ICE | Dan Ravensloft | 2020-04-23 | 1 | -0/+12 | |
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| * | tests: read +/xilinx/cell_sim.v before xilinx_dsp test | Eddie Hung | 2020-04-22 | 1 | -0/+1 | |
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| * | test: ice40_dsp test to read +/ice40/cells_sim.v for default params | Eddie Hung | 2020-04-22 | 1 | -0/+1 | |
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| * | xilinx: xilinx_dffopt to read cells_sim.v; fix test | Eddie Hung | 2020-04-22 | 1 | -13/+22 | |
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| * | Merge pull request #1949 from YosysHQ/eddie/select_blackbox | Eddie Hung | 2020-04-22 | 1 | -0/+28 | |
| |\ | | | | | select: do not select inside black-/white- boxes unless '=' prefix used | |||||
| | * | tests: update select black/white-box tests | Eddie Hung | 2020-04-22 | 1 | -0/+7 | |
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| | * | select: add test for not selecting inside black/white boxes | Eddie Hung | 2020-04-16 | 1 | -0/+21 | |
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| * | | Merge pull request #1973 from YosysHQ/eddie/fix1966 | Eddie Hung | 2020-04-22 | 1 | -1/+3 | |
| |\ \ | | | | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share | |||||
| | * | | tests: use `yosys-config --datdir` instead of hard-coded | Eddie Hung | 2020-04-22 | 1 | -1/+3 | |
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| * | | | Merge pull request #1950 from YosysHQ/eddie/design_import | Eddie Hung | 2020-04-22 | 2 | -5/+22 | |
| |\ \ \ | | | | | | | | | design: -import to not count black/white-boxes as candidates for top | |||||
| | * | | | design: add test | Eddie Hung | 2020-04-16 | 2 | -5/+22 | |
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| * | | | Merge pull request #1976 from YosysHQ/dave/fix-sim-const | Claire Wolf | 2020-04-22 | 1 | -0/+13 | |
| |\ \ \ | | | | | | | | | sim: Fix handling of constant-connected cell inputs at startup | |||||
| | * | | | sim: Fix handling of constant-connected cell inputs at startup | David Shah | 2020-04-21 | 1 | -0/+13 | |
| | | |/ | |/| | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | hierarchy: Convert positional parameters to named. | Marcelina Kościelnicka | 2020-04-21 | 1 | -0/+23 | |
| | | | | | | | | | | | | | Fixes #1821. | |||||
| * | | | Merge pull request #1851 from YosysHQ/claire/bitselwrite | Claire Wolf | 2020-04-21 | 13 | -0/+1224 | |
| |\ \ \ | | | | | | | | | Improved rewrite code for writing to bit slice | |||||
| | * | | | Remove '-ignore_unknown_cells' option from 'sat' | Eddie Hung | 2020-04-20 | 1 | -6/+6 | |
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| | * | | | Simplify test case script | Eddie Hung | 2020-04-20 | 1 | -30/+17 | |
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| | * | | | Remove ununsed files | Eddie Hung | 2020-04-20 | 5 | -83/+0 | |
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| | * | | | Modifications of tests as per Eddie's request | diego | 2020-04-20 | 15 | -78/+1237 | |
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| | * | | | Wrong fixed value | diego | 2020-04-17 | 1 | -1/+1 | |
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| | * | | | Adding tests for dynamic part select optimisation | diego | 2020-04-16 | 7 | -0/+161 | |
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| * | | | | tests: remove write_ilang | Eddie Hung | 2020-04-20 | 2 | -3/+0 | |
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| * | | | | abc9: add testcase reduced from #1970 | Eddie Hung | 2020-04-20 | 1 | -0/+19 | |
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| * | | | tests: add select -unset tests | Eddie Hung | 2020-04-16 | 2 | -0/+20 | |
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| * | | tests: add design -delete tests | Eddie Hung | 2020-04-16 | 2 | -0/+18 | |
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| * | | Merge pull request #1943 from YosysHQ/dave/fix-1919 | David Shah | 2020-04-16 | 1 | -0/+18 | |
| |\ \ | | | | | | | ast: Fix handling of identifiers in the global scope | |||||
| | * | | ast: Fix handling of identifiers in the global scope | David Shah | 2020-04-16 | 1 | -0/+18 | |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * / | opt_expr: Fix X and CO outputs for $alu identity-mapping rules. | Marcelina Kościelnicka | 2020-04-16 | 1 | -8/+66 | |
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| * | Merge pull request #1933 from YosysHQ/eddie/zinit_more | Eddie Hung | 2020-04-15 | 1 | -2/+96 | |
| |\ | | | | | zinit: handle $__DFFS?E?_[NP][NP][01] too | |||||
| | * | tests: zinit for new types | Eddie Hung | 2020-04-14 | 1 | -2/+96 | |
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| * | | Merge pull request #1930 from YosysHQ/claire/fix1876 | Claire Wolf | 2020-04-15 | 1 | -0/+60 | |
| |\ \ | | | | | | | Fix handling of ternary with constant condition | |||||
| | * | | tests: add testcases from #1876 | Eddie Hung | 2020-04-14 | 1 | -0/+60 | |
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| * | | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 10 | -0/+208 | |
| | | | | | | | | | | | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6). | |||||
| * | | opt_expr: Add more $alu optimizations. | Marcelina Kościelnicka | 2020-04-14 | 1 | -4/+52 | |
| |/ | | | | | | | | | | | Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912. | |||||
| * | dffinit: Avoid setting init parameter to zero-length value. | Marcelina Kościelnicka | 2020-04-14 | 1 | -0/+25 | |
| | | | | | Fixes #1704. | |||||
| * | Merge pull request #1879 from jjj11x/jjj11x/package_decl | whitequark | 2020-04-14 | 1 | -3/+8 | |
| |\ | | | | | support using previously declared types/localparams/parameters in package | |||||
| | * | support using previously declared types/localparams/params in package | Jeff Wang | 2020-04-07 | 1 | -3/+8 | |
| | | | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also) | |||||
| * | | zinit: resolve one more comment by @mwkmwkmwk | Eddie Hung | 2020-04-13 | 1 | -1/+8 | |
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