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* Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-247/+0
| | | | | This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
* Add a couple more testsEddie Hung2019-06-121-0/+12
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* Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into ↵Eddie Hung2019-06-122-53/+0
| | | | | | | xc7mux" This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2.
* Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-41/+0
| | | | | This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
* Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-102-0/+53
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| * Add testEddie Hung2019-06-102-0/+53
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-101-1/+6
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| * Add some more commentsEddie Hung2019-06-101-1/+6
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-0728-33/+138
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| * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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| * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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| * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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| * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
| |\ | | | | | | elaboration system tasks
| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+31
| | |\ | | | | | | | | | | | | clifford/pr983
| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-074-3/+42
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-062-0/+41
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| * | | | Fix and test for balanced caseEddie Hung2019-06-062-0/+41
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* | | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-0615-0/+512
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| * | | | Fix warningsEddie Hung2019-06-062-3/+3
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| * | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
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| * | | | Add non exclusive testEddie Hung2019-06-062-0/+56
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| * | | | One more and tidy upEddie Hung2019-06-062-6/+28
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| * | | | Add a few more special case testsEddie Hung2019-06-062-0/+51
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| * | | | Add tests, fix for !=Eddie Hung2019-06-062-0/+78
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| * | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
| |/ / | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-0/+4
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| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
| |\ \ | | | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Rename to #23Eddie Hung2019-05-291-3/+3
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* | | | Add abc_test024Eddie Hung2019-05-291-6/+19
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* | | | Add abc9_test022Eddie Hung2019-05-281-0/+22
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* | | | From masterEddie Hung2019-05-281-1/+1
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* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-283-27/+84
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| * | | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| | * | Fix initEddie Hung2019-05-241-27/+27
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| | * | Fix typosEddie Hung2019-05-241-6/+6
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| | * | Add more testsEddie Hung2019-05-242-20/+41
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| | * | Call procEddie Hung2019-05-241-1/+1
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| | * | Fix duplicate driverEddie Hung2019-05-241-15/+15
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| * | | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
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| * | | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
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| * | | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
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* | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-232-0/+55
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