iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20	1	-0/+48
*	Implemented indexed part selects	Clifford Wolf	2013-11-20	1	-0/+5
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-0/+41
*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18	1	-0/+28
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18	1	-0/+22
*	Fixed handling of power operator	Clifford Wolf	2013-11-07	1	-0/+15
*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...	Clifford Wolf	2013-11-02	1	-6/+6
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02	1	-0/+7
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24	1	-12/+26
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21	1	-0/+39
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	3	-5/+5
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12	1	-24/+29
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09	2	-24/+43
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12	1	-0/+8
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12	1	-0/+8
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11	1	-0/+7
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09	1	-13/+15
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09	2	-2/+20
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	2	-2/+20
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09	1	-3/+43
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-0/+10
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07	13	-1748/+0
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05	3	-2/+14
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05	1	-6/+23
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05	1	-4/+5
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05	1	-0/+13
*	Added xsthammer report generator	Clifford Wolf	2013-07-05	4	-13/+170
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04	2	-1/+484
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04	3	-14/+115
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+16
*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03	3	-2/+39
*	Progress in xsthammer	Clifford Wolf	2013-07-03	5	-9/+23
*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26	5	-7/+69
*	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20	1	-2/+2
*	Added "eval" pass	Clifford Wolf	2013-06-19	1	-2/+2
*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17	2	-2/+175
*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15	1	-7/+124
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	1	-2/+7
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13	5	-69/+49
*	Another fix for a bug found using xsthammer	Clifford Wolf	2013-06-12	1	-4/+8
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	6	-138/+226
*	More xsthammer improvements	Clifford Wolf	2013-06-10	2	-21/+27
*	Progress xsthammer scripts	Clifford Wolf	2013-06-10	3	-27/+37
*	Progress in xsthammer: working proof for cell models	Clifford Wolf	2013-06-10	3	-34/+51
*	Progress on xsthammer	Clifford Wolf	2013-06-10	5	-0/+268
*	Added first xsthammer scripts	Clifford Wolf	2013-06-10	4	-0/+183
*	Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v	Clifford Wolf	2013-05-24	1	-1/+3
*	Removed test cases that have been moved to yosys-test.	Clifford Wolf	2013-05-17	83	-18963/+0
*	Improved vcdcd.pl (added -d option)	Clifford Wolf	2013-05-14	1	-8/+82
*	Some improvements in vcdcd.pl	Clifford Wolf	2013-05-14	1	-4/+16