diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-05-24 15:15:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-05-24 15:15:59 +0200 |
| commit | cc0540412832859d28e5c24c8be95c725c10ed19 (patch) | |
| tree | a62cdb3cd5c42ef455196dc1925ec9bb6406081f /tests | |
| parent | 66bc46b30b13ce6f9005edff7a479e28f223a678 (diff) | |
| download | yosys-cc0540412832859d28e5c24c8be95c725c10ed19.tar.gz yosys-cc0540412832859d28e5c24c8be95c725c10ed19.tar.bz2 yosys-cc0540412832859d28e5c24c8be95c725c10ed19.zip | |
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_fsm_full_tb.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v index 0097b1c98..2e9448950 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v @@ -4,11 +4,13 @@ reg req_0 , req_1 , req_2 , req_3; wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ; initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); $display("Time\t R0 R1 R2 R3 G0 G1 G2 G3"); $monitor("%g\t %b %b %b %b %b %b %b %b", $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); clock = 0; - reset = 0; + reset = 1; req_0 = 0; req_1 = 0; req_2 = 0; |