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* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
|\ | | | | Add -select option to aigmap
| * Add quick testEddie Hung2019-09-301-0/+10
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* | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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* | Add testEddie Hung2019-09-301-0/+16
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* Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-306-0/+152
|\ | | | | rpc: new frontend
| * rpc: new frontend.whitequark2019-09-306-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
* | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
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* | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2910-11/+325
|\ \ | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-231-0/+62
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| * | | Add more complicated macc testcaseEddie Hung2019-09-192-5/+39
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| * | | Add mac.sh and macc_tb.v for testingEddie Hung2019-09-192-0/+99
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| * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-0/+41
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| * | | | Format macc.vEddie Hung2019-09-191-8/+8
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| * | | | Remove statEddie Hung2019-09-181-1/+0
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| * | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-181-2/+26
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| * | | | | Add .gitignoreEddie Hung2019-09-181-0/+1
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| * | | | | Refine macc testcaseEddie Hung2019-09-182-9/+17
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-123-1/+63
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| * | | | | | Add AREG=2 BREG=2 testEddie Hung2019-09-111-2/+6
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| * | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-0/+71
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| * | | | | | | Update test with a/b resetEddie Hung2019-09-111-2/+4
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| * | | | | | | Extend test for RSTP and RSTMEddie Hung2019-09-112-3/+50
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-1/+18
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| * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-6/+6
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| * \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-112-7/+105
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| * | | | | | | | | | Add SIMD testEddie Hung2019-09-091-0/+25
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| * | | | | | | | | | Update macc testEddie Hung2019-09-062-42/+42
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| * | | | | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-052-21/+63
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| * \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+3
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| * \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-041-0/+8
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| * \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-045-9/+39
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| * | | | | | | | | | | | | | Add macc test, with equiv_opt not currently passingEddie Hung2019-08-302-0/+54
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| * | | | | | | | | | | | | | Update test for ffMEddie Hung2019-08-301-2/+2
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| * | | | | | | | | | | | | | Add mul_unsigned testEddie Hung2019-08-302-0/+41
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* | | | | | | | | | | | | | | Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396.
* | | | | | | | | | | | | | | Change order of parameters, to work on other osMiodrag Milanovic2019-09-271-1/+1
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* | | | | | | | | | | | | | Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40Eddie Hung2019-09-252-19/+14
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | ICE40 tests. adffs test update (equiv_opt -multiclock).
| * | | | | | | | | | | | | Change sync controls to async.SergeyDegtyar2019-09-252-8/+8
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| * | | | | | | | | | | | | adffs test update (equiv_opt -multiclock).SergeyDegtyar2019-09-242-18/+13
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* | | | | | | | | | | | | | Hell let's add the original #1381 testcase tooEddie Hung2019-09-201-3/+22
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* | | | | | | | | | | | | | Add testcaseEddie Hung2019-09-201-0/+43
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* | | | | | | | | | | | | Added extractinv passMarcin Kościelnicki2019-09-191-0/+41
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* | | | | | | | | | | | Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxextEddie Hung2019-09-182-13/+175
|\ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
| * | | | | | | | | | | OopsEddie Hung2019-09-131-1/+1
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| * | | | | | | | | | | Add counter-example from @cliffordwolfEddie Hung2019-09-131-0/+24
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| * | | | | | | | | | | Revert "Make one check $shift(x)? only; change testcase to be 8b"Eddie Hung2019-09-131-2/+2
| | |_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80.
| * | | | | | | | | | Cope with presence of reset muxes tooEddie Hung2019-09-111-0/+39
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| * | | | | | | | | | Add more testsEddie Hung2019-09-111-0/+32
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| * | | | | | | | | proc instead of prepEddie Hung2019-09-111-2/+2
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| * | | | | | | | | Add unsigned caseEddie Hung2019-09-111-0/+17
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